[SOLVED] extract non-standard number of LS bits from std_logic_vector in vhdl

[alkaios]

hello! i have a problem in vhdl and i hope you can help me

i want to take LS bits from a signal, but the number of these bits it's not certain.
to be more specific, i want to do this:

a <= b(x-1 downto 0).

a, b, x are std_logic_vectors. x is calculated somewhere else in my program.
range of a should be x bits, range of b is 54 bits, range of x is 8 bits.

i already tried something obvious:

signal xx : integer range 0 to 7 := TO_INTEGER(UNSIGNED(x));
signal a : std_logic_vector(xx-1 downto 0);
a <= b(xx-1 downto);

but it doesn't work. any suggestions? is there any attribute or function that can help?
thanx in advance.

 

[FvM]

but it doesn't work

Yes, by VHDL specification vector slices must have a constant range. There's also another thing that doesn't work, bit lengths of expression left and right side must be equal.

Single bits can be however selected by a variable index, thus there are several ways to do what you want. I prefer a for loop iteration or generate statement over the maximum index range (iteration ranges must be constant as well), enabling the actual wanted bits with a conditional assignment.

 

[alkaios]

Yes, by VHDL specification vector slices must have a constant range. There's also another thing that doesn't work, bit lengths of expression left and right side must be equal.

Single bits can be however selected by a variable index, thus there are several ways to do what you want. I prefer a for loop iteration or generate statement over the maximum index range (iteration ranges must be constant as well), enabling the actual wanted bits with a conditional assignment.

thank you for your immediate response. unfortunately i can't understand you completely. could you be more specific?
for example, in for loop the desired iteration range should be x, how would i make it constant, and how this would be helpful? (value of x is computed in another component and comes as input to this component)
as for generate, i have only used it for multiple instantiations, how could i use it in this problem?

 

[FvM]

Consider a construct like:

for i in b'low to b'high loop
  if i < x then
    a(i) <= b(i);
  end if;
end loop;

 

[alkaios]

i just did it, and it worked!
thank you very much! you saved my day