P total power dissipation= P dynamic switching power + P short-circuit power + P static biasing power + P leakage power.
P dynamic switching power
CMOS circuits dissipate power by charging the various load capacitances whenever they are switched. Power is dissipated across the PMOS transistor while the load capacitor is being charged and across the NMOS when the load capacitor is being discharged. Power consumption depends upon switching frequency, load capacitance, and supply voltage.
P short-circuit power
Due to direct current path from Vdd to ground during output switching
P static biasing
Are related to the current that flows when the gate terminals are not changing.
Ideally CMOS circuits do not present static power dissipation. However, real systems present degraded voltage levels feeding CMOS gates and a current flow from the power supply to ground nodes is observed.
P leakage power
Due to subthreshold & gate leakage
More details about
Low Power Design
https://inf.ufrgs.br/logics/docman/book_emicro_butzen.pdf