Explanation of the TLP testing method

[dennislau]

Now, the TLP testing method is going to be more and more popular in analyzing the ESD devices. For this new testing method, I have several questiions related to this, does anyone can help me? Thanks.

Do the TLP testing results always correlate with the HBM/MM/CDM zapping test results? I found there is a correlation factor between TLP and HBM/MM/ CDM, does it always a constant or varying with different process/foundry and varying with different ESD circuits (such as diode, ggNMOS, active clamp......)? And, how to find this correlation factor correctly?

 

[scottieman]

Re: TLP testing method

Now, the TLP testing method is going to be more and more popular in analyzing the ESD devices. For this new testing method, I have several questiions related to this, does anyone can help me? Thanks.

Do the TLP testing results always correlate with the HBM/MM/CDM zapping test results? I found there is a correlation factor between TLP and HBM/MM/ CDM, does it always a constant or varying with different process/foundry and varying with different ESD circuits (such as diode, ggNMOS, active clamp......)? And, how to find this correlation factor correctly?

I am also new on this topic. However, let me share what I know to you here

TLP (for someone who wants to know, is Tranmission Line Pulsed) method is a new setup to test ESD device. Why people try to develope TLP? It is because people believe (or have proved, I don't know) TLP can emulate the real ESD event (e.g. our finger touch a pin of a IC) than the other models such as HBM, MM and CDM.

The results are a ESD device is passed from a TLP test will be said more sustainable to real world ESD events than other devices passing the HBM and MM test.

Scottie

 

[dennislau]

Re: TLP testing method

I found some useful information about the TLP recently and share with you

 

[DoctorProf]

Re: TLP testing method

TLP is a very important tool for the ESD Design Engineer and for ESD Protection design. TLP allows you to see the I-V characteristics of a device. From this you have a much better idea of what the current and voltage relationship is so you can meet the ESD design window.

It has been my experience that HBM and TLP correlate most of the time. When they do not correlate it is because of the parasitic elements that exist in the HBM tester providing extra current pulses or voltage pulses.

Coorelation with MM and CDM is not as good. Typically you can take the HBM results and divide by 10 to 20x to get the MM. CDM is not nearly as easy. For CDM the industry is coming out with VF-TLP (Very Fast TLP). This simulates the very fast transients seen in CDM.

DrProf

 

[dennislau]

Re: TLP testing method

TLP is a very important tool for the ESD Design Engineer and for ESD Protection design. TLP allows you to see the I-V characteristics of a device. From this you have a much better idea of what the current and voltage relationship is so you can meet the ESD design window.

It has been my experience that HBM and TLP correlate most of the time. When they do not correlate it is because of the parasitic elements that exist in the HBM tester providing extra current pulses or voltage pulses.

Coorelation with MM and CDM is not as good. Typically you can take the HBM results and divide by 10 to 20x to get the MM. CDM is not nearly as easy. For CDM the industry is coming out with VF-TLP (Very Fast TLP). This simulates the very fast transients seen in CDM.

DrProf

Thanks very much DrProf and your feedback is helpful to me.

For this, I have some following questions, you mentioned that typically, we can take the HBM results and divide by 10 to 20x to get the MM. How to determine this number and does this number depends on process/technology such as 0.35u, 0.25u technology?

 

[DoctorProf]

Re: TLP testing method

The TLP system (Current pulse with similar rise time to HBM and pulse duration of 100ns) was targeted to match the damage an HBM pulse of the same peak current would produce. This implies that a 3K HBM would produce a 2 amp peak current (3000 volts divided by the 1500 ohm resistor in the model). This is the matching that was done early in the TLP development.

MM and HBM are similar models with the MM being like a worst case HBM model (someone sitting (2x capacitance) holding a metalic tool (zero ohm resistance) in their hand contacting the part. I'm not sure there was a exhastive evaluation of the relationship between MM and HBM but it has become an general rule. For older technology (> 0.5um) I find 10x to be the norm. A part that passes 2000 HBM will typically be > 200 MM. Many companies do not test for MM any longer because they feel it is redundant to test both MM and HBM. For newer technologies I'm seeing a trend that it is more like 15x or 20x. I believe this is because it is not so much the energy content that is causing the damage but the difference in the peak currents between MM and HBM. MM is affected by the package parasitics (resistance and inductance) and by the protection elements dynamic resistance. HBM looks more like a pure current source with a define waveform (double exponential, fast rise; 150ns time constant decay).

DrProf

 

[dennislau]

Re: TLP testing method

The paper in Taiwan ESD Conference 2005 "Circuit and Silicide Impact on the Correlation Between TLP and ESD (HBM and MM)” discuss issues about the miscorrelation between the TLP and ESD zapping testing results in some cases. It was found that when with silicide ESD devices, TLP measurement would not correlate to ESD zapping results while for non-silicide ESD devices (with silicide block), TLP measurement correlate well with ESD zapping results.

 

[mosfet_man]

TLP testing method

Question to DrProf

Do your think ESD performance is strong related to latch up?

 

[oxynitride]

Re: TLP testing method

look at the recent ESREF proceedings - one of the best papers which talks about TLP to HBM comparison matter. i will try to upload it sometime next week (need to get the CDROM from my prof).
TLP-HBM ratio is 1,5 since TLP is 100ns and HBM is 150ns. But this means nothing in the present day technologies. also, TLP is not a method for qualifying full products. so my prof says, this is waste of everyones time. rise time effects, switch on behaviours, etc. all depends on the pulse natuure. so should it compare?
greets
Oxy

 

[DoctorProf]

Re: TLP testing method

ESD can be inversely related to latchup but latch-up and ESD should be seperate issues and addressed with seperate design methods.

The inverse relationship is related to substrate resistance. The easier a part can enter latchup usually means it will provide better ESD protection (parasitic NPN in NMOS turns on easier). As you thin the epi layer or decrease its resistance you reduce the latchup risk but make the NPN harder to turn on.

Latchup is driving by proper layout and collection of any minority carriers that are injected into the substrate before they interact with adjacent diffusions. This is accomplished by proper guard ring structures and the proper spacing between structures.

I'm interested in getting access to the ESREF proceedings. How is the best way to get access to these documents.

DrProf

 

[Anbusivam]

Re: TLP testing method

Hello All,

Can you please give me some waveforms on TLP testing.

How is voltage levels up to 2Kv is acheived...?

Regards,
Anbu