Explanation of the code

[xilinx1001]

Hi,

Can anyone please tell me, why only 13 to 23 bits are taken in this code for distance measurement

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity distance_measurer is
    port ( clk : in  STD_LOGIC;
      trigg : in STD_LOGIC;
           pulse : in  STD_LOGIC;
           distance : out  STD_LOGIC_VECTOR(8 downto 0) := (others => '0') );
end distance_measurer;
architecture Behavioral of distance_measurer is
 component Counter is
   generic(n : POSITIVE := 10);
   Port ( clk : in  STD_LOGIC;
      en : in  STD_LOGIC;
      reset : in  STD_LOGIC;   -- Active Low
      output : out  STD_LOGIC_VECTOR(n-1 downto 0) );
 end component;
 signal CounterPulseOut : STD_LOGIC_VECTOR(21 downto 0);
begin
 CounterPulse : Counter generic map(22) 
March 18, 2011 1 Aart Mulder and Kol
    port map(clk,pulse,not trigg,CounterPulseOut);

 DistanceProcess : process(pulse,CounterPulseOut)
  variable temp : integer;
variable tempVar : STD_LOGIC_VECTOR(23 downto 0);
 begin
   if(pulse'event and pulse = '0') then
    tempVar :=  CounterPulseOut * "11";
    temp := to_integer(unsigned(tempVar(23 downto 13)));
    if(temp > 458) then
     distance <= "111111111";
    else        
     distance <= STD_LOGIC_VECTOR(to_unsigned(temp,9))
    end if;
   end if;
 end process DistanceProcess;
end Behavioral;