when our using DC, clk consists of real clock and virtual clock ,real clock has its source, virtual has not its source, we can define input and output's relative delay by using virtual as referrence clock, it also useful in constraining comb logic.
Instead of using set_max_delay to constraint ur combo block, u can use virtual clock and use set_input_delay and set_output_delay, which can decreases runtime and memory usage in DC.
Instead of using set_max_delay to constraint ur combo block, u can use virtual clock and use set_input_delay and set_output_delay, which can decreases runtime and memory usage in DC.
How will you constraint the combinational delay by virtual clock and with set_input_delay and set_output_delay. How does it decrease runtime and memory usage?
How will you constraint the combinational delay by virtual clock and with set_input_delay and set_output_delay. How does it decrease runtime and memory usage?
Just write a simple logic: assign mul[31:0] = a[15:0] * b[15:0]. Then:
1): define virtual clock and input/output delay, related to the virtual clock.
2): report input and output timing, and area.
3): change virtual clock period and input/output delay value, and re-synthesis the same design again.
4): report input and output timing, and area.
Then you will know how it works.
Engineering are not just on theory, but also need tried it out.