Explain me concept of virtual clock in constraining design

[dak-ju]

virtual clock

Hi
can anyone explain me the concept of virtual clock in constraining a design?

Regards
dak-ju

 

[dolby.yang]

Re: virtual clock

when our using DC, clk consists of real clock and virtual clock ,real clock has its source, virtual has not its source, we can define input and output's relative delay by using virtual as referrence clock, it also useful in constraining comb logic.

 

[no_mad]

virtual clock

additional info for virtual clock:

Instead of using set_max_delay to constraint ur combo block, u can use virtual clock and use set_input_delay and set_output_delay, which can decreases runtime and memory usage in DC.

Hope this helps

 

[silverbyte]

Re: virtual clock

There is a good post on Virtual clocks at
https://loxos.blogspot.com/2005/04/timinganalysis-why-virtual-clocks.html

What do you think of this explanation?

 

[dBUGGER]

Re: virtual clock

There is a good post on Virtual clocks at
h**p://loxos.blogspot.com/2005/04/timinganalysis-why-virtual-clocks.html

What do you think of this explanation?

Hi,
ya quite nice. But please tell me how do you declare virtual clocks and associate the same with any flip-flop.

Best Regards,

 

[dak-ju]

Re: virtual clock

There is a good post on Virtual clocks at
h**p://loxos.blogspot.com/2005/04/timinganalysis-why-virtual-clocks.html

What do you think of this explanation?

Hi,
ya quite nice. But please tell me how do you declare virtual clocks and associate the same with any flip-flop.

Best Regards,

Hi,
Defining virtual clock is simple. Do it as below :
create_clock -name "clk_virtual" - period <value> -waveform {0 x}

Best Regards,
dak-ju

 

[eeeraghu]

Re: virtual clock

create_clock -name "clk_virtual" - period <value> -waveform {0 x}

This is fine but i believe this command is used in design compiler, what about other EDA tools, is it possible to use it in other EDA tools?

 

[spauls]

Re: virtual clock

virtual clocks is used to constrain combinational logic,
you can also constraint I/o wrt virtual clock , in order to get latency for real clock.

 

[beckchm]

Re: virtual clock

It is for the combinational logic.

 

[jasonkee111]

Re: virtual clock

I am not really understanding on it. Can you provide some diagram and explanation.

Your effort is much appreciated.

thanks

 

[ivlsi]

you can also constraint I/o wrt virtual clock , in order to get latency for real clock

How do you do that?

 

[sun_ray]

Re: virtual clock

additional info for virtual clock:

Instead of using set_max_delay to constraint ur combo block, u can use virtual clock and use set_input_delay and set_output_delay, which can decreases runtime and memory usage in DC.

Hope this helps

How will you constraint the combinational delay by virtual clock and with set_input_delay and set_output_delay. How does it decrease runtime and memory usage?

 

[yx.yang]

Re: virtual clock

How will you constraint the combinational delay by virtual clock and with set_input_delay and set_output_delay. How does it decrease runtime and memory usage?

Just write a simple logic: assign mul[31:0] = a[15:0] * b[15:0]. Then:
1): define virtual clock and input/output delay, related to the virtual clock.
2): report input and output timing, and area.
3): change virtual clock period and input/output delay value, and re-synthesis the same design again.
4): report input and output timing, and area.

Then you will know how it works.

Engineering are not just on theory, but also need tried it out.