Advanced Member level 3
Can anyone please provide example of paths that are not treated as false paths although they are path crossing from one clock domain to another clock domain?
Data within DDR PHY.
Need shift the DQs to capture DQ (named as dq_reg), then, dq_reg will be transfered to clock domian in the chip (this can't be a false path while transfer between 2 clock domains).
in clock domain crossing, you set false path for hold while doing synthesis because two clocks are asynchronous and timing cannot checked.
But you set set_max_delay and set_min_delay on these paths. so that data should reach after specified delay.
Please note it may be derived clock..