example of path for multi clock design

[sun_ray]

Can anyone please provide example of paths that are not treated as false paths although they are path crossing from one clock domain to another clock domain?

 

[asic_service]

Data within DDR PHY.
Need shift the DQs to capture DQ (named as dq_reg), then, dq_reg will be transfered to clock domian in the chip (this can't be a flase path while transfer between 2 clock domains).

 

[sun_ray]

Data within DDR PHY.
Need shift the DQs to capture DQ (named as dq_reg), then, dq_reg will be transfered to clock domian in the chip (this can't be a false path while transfer between 2 clock domains).

Can you please elaborate the path in detail with an diagram so that what you want to say is understood well? How does the path look like? What kind of combinational logic will be there in that path? Why is it necessary to check the timing of such a path such that false path cannot be set?

 

[rocking_vlsi]

in clock domain crossing, you set false path for hold while doing synthesis because two clocks are asynchronous and timing cannot checked.

But you set set_max_delay and set_min_delay on these paths. so that data should reach after specified delay.

 

[vijayR15]

Hai sunray,

Please note it may be derived clock..

 

[sun_ray]

in clock domain crossing, you set false path for hold while doing synthesis because two clocks are asynchronous and timing cannot checked.

But you set set_max_delay and set_min_delay on these paths. so that data should reach after specified delay.

How does it answer my question?

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Hai sunray,

Please note it may be derived clock..

I am asking example of path. How does your reply answer my question?

 

[mail4idle2]

Lets say there are two state machines. 1st state machine runs on clock1 and 2nd state machine runs on clock 2. In design after 1ststate machine is completed you have to move to 2nd state machine. You have to pass a signal from 1st state machine to inform 2nd state machine to start.

Tell me whether it answered your question or not ?

 

[ads_ee]

sun_ray,

Here is an example...

**broken link removed**

As clk_1x and clk_2x are phase locked, the setup/hold time between Reg 1 and Reg 2 is not a false path. Place and route tools should be able to compensate for any clock skew between the two clock domains to meet both setup and hold time.

Yes, you could treat it as asynchronous, but that would then require synchronization registers at the output of Reg 1 clocked on clk_2x. These synchronization registers wouldn't be doing much besides compensating for skew introduced due to a false_path placed on the clock crossing. Depending on the clock skew involved the first synchronization register could experience continuous metastable events if the skew results in the data arriving at the syncrhonization register coincident with the clock edge. So by using a false path in this case we might actually make things more likely to go metastable. 8-O