Every well must have at least one well tap(again

[junsik]

DRC rule about well tap

hi i have some problem about DRC check
when I run DRC, blow statement was shown.
"Every well must have at least one well tap"

How can I solve the problem??
What kind of component should be inserted in the layout?

Thank you.

 

[KlausST]

Re: DRC rule about well tap

Hi,

what software are you referring to?
Are you sure this is the exact error description?

Try to give more detailed information.

Klaus

 

[erikl]

Re: DRC rule about well tap

"Every well must have at least one well tap"
1. How can I solve the problem??
2. What kind of component should be inserted in the layout?

1. Do exactly what the error message says: include at least one well-tap into each well region.
2. A well-tap (in case of an n-well) is an n⁺ diffusion in the n-well, connected by a contact to metal1 and then to VDD.

 

[jmh6265]

I'm a college of jusik, who made an article on this forum.
He asked about DRC error "Every well must have at least one well tap"
I want to ask you about our problem more precisely.
1) First, we tried using NW(N-well) layer to make a GDPMOS(Ground-Vdd PMOS). During DRC, the error 'Every well must have at least one well tap' occurred.
However, I already made a n+ diffusion, whose layer name is 'NACT' in the design rule I have.
2) I didn't use instance to make body tap. I just hard copied a NMOS(which is specially made for ESD protection devices) from other file(this doesn't have macro) and changed all of the layers' properties to make PMOS. <- Can this make a problem?
3) Although the DRC of this GDPMOS failed, when I use this GDPMOS in other schematics or layouts as 'instance', there was no DRC or LVS error!
4) When I made a GGNMOS(Gate-Grounded NMOS), there was no error with PACT(p+). DRC and LVS was successful for GGNMOS.

 

[vijaya.kumar]

can you show the error message where it is occurring ex: snap shot.

 

[dick_freebird]

Are you sure that (a) NACT by itself produces a N+ region
and (b) you have it connected (according to extract rule
logic) to metal?

Try using the utility that displays your mask layers from the
mask fab Booleans, if your local setup has this, and see if
you've got everything in the vertical stack that makes an
ohmic tie.

 

[jmh6265]

Thanks for everyone who replied, and I will check whether if the NACT is really connected to metal or not.