Estimating number of Multiplication with FIR filter

[seeking_help]

Hi,

I am having some difficulties with working out the following question. Any help or guide to solve these questions are deeply appreciated. Thank You

Given a set of specification for an FIR Low Pass Filter:

Sampling Frequency = 18Khz
Passband Edge = 250 Hz
Stopband Edge = 350 Hz
Passband Ripple = 1 dB
Stopband Attenuation > 80 dB

1) What is the best estimate of the number of multiplications per second required to process this data with a standard transverse FIR filter ( Based on the harris forumale for filter length)?

2) What is the maximum downsampling factor which could be applied to the output of this filter without significant aliasing distortion?

3) What is the best estimate of the number of multiplications per second required to process this data with a polyphase downsampling filter?

 

[hobgoblin]

1) What is the best estimate of the number of multiplications per second required to process this data with a standard transverse FIR filter ( Based on the harris forumale for filter length)?

I don't know what the harris formula is, but you have to design an LPF satisfying your criteria at first. The length of the designed filter will uniquely determine the number of MAC operations required to implement it.

2)What is the maximum downsampling factor which could be applied to the output of this filter without significant aliasing distortion?

As the low-pass filtering is applied before downsampling the part of the spectrum above 350 Hz will not contain spectral components that could deteriorate in-band performance after aliasing (assuming that 80 dB suppression of aliased components is acceptable). Therefore the upper limit of the (integer) downsampling factor is ceil(18000/(350*2)) = 25.

3) What is the best estimate of the number of multiplications per second required to process this data with a polyphase downsampling filter?
The polyphase implementation can be very effective if you design a hardwired filter (in FPGA or ASIC) since it allows reducing the number of multipliers, however the total number of multiplication operations stays the same. In can also give benefits when the filtering is performed in software, but i'm afraid i can't tell you more, cause i've designed polyphase filters in VHDL only.

PS: MACS (multiply-accumulate per second) is not a property of an algorithm, it is a property of a processor. I.e. if processor has processing speed of say X MACS and your input data have the sample rate of N Hz then the number of filter taps you can implement (ignoring overheads associated with interrupt management and so on) is X/N.