errors when using PrimeTime-PX

[cashen224]

Hi

I am a new comer in ASIC design. I am now trying to use PrimeTime-PX for (post-synthesis) timing analysis and power estimation.

I saw a lot of errors like following error message while executing PT:

"Error: No net timing arc from pin 'U555/Q' to pin 'path_metric_compute/add_87/U1_14/B'. (PTE-014) ".

I guess the library or import files I sent to PT were wrong since it looks like all the paths were wrong. I sent nestlist, .sdf file, .sdc file, and .spef file from DC to the PT and I am using Synopsys education 90nm library (SAED90nm Library).

Could you please advise me what could be the problem causing this? I really appreciate any help.

 

[yadavvlsi]

Create an account on https://solvnet.synopsys.com/. It is synopsys support website. It will help you during your initial stage and for future also..!

 

[wsong0210]

Seems like your .v file does not match with your .sdf file. Check which one is not updated to the new version.

 

[cashen224]

Thanks for all the helps.

I just realized that there is a version mismatch between DC and PT. I used newer version of DC than PT.

 

[wsong0210]

Personally I dont think the version mismatch is a problem unless the version is mismatched too much (like more than 3 major version difference)

 

[michealwolf]

Hi,

How do you back annotate the design, SPEF or SDF?
It probablly because of mismatches of SPEF/SDF vs NETLIST.
Or you used some wrong commands that constrains the non-exists timing arcs.