electrobuz
Member level 2
I am trying to debug a design using Nios II on a Stratix V FPGA. When debugging with system-console, while trying to do a memory read, i get the following error :
The RAM in my design doesn´t seem to work. How can I solve this?
% master_read_memory $nios 0x00000 4
error: master_read_memory: com.altera.systemconsole.internal.plugin.jtag.oci.Nios2DebugException: Target is broken and needs to be reset while executing
The RAM in my design doesn´t seem to work. How can I solve this?