error when simulating in modelsim

[vishwasgowda]

Illegal output or inout port connection (port 'out1')....can any one help me out

 

[rajavel.rv]

Illegal output or inout port connection (port 'out1')....can any one help me out

send clear details about your error, post with your written code and identify where is the bug.

 

[vishwasgowda]

send clear details about your error, post with your written code and identify where is the bug.

the program contains two functions ....i.e a comparator and a counter....each of these functions are called 256 times in the main module.....i am instantiating both of these functions 256 times in the main module...
The input to all comparators is one common input din and one constant input....
output of comparator is an enable signal which is an input to counter...there are 256 counters hence 256 enable signals from 256 comparators i.e, en0, en1, en2....en255....i have declared enable signal as wire... the final output has 256 ouputs from each of the 256 counters i.e, dout0, dout1, dout2...dout255...it is an 8 bit output...i have declared it as [7:0] output as well as type [7:0] reg....

comparator u0 (din , 8'd0 , en0);
comparator u1 (din , 8'd1 , en1);
comparator u2 (din , 8'd2 , en2);
'
'
'
comparator u255 (din , 8'd2 , en255);


counter s0 (en0 , clk , reset_n , dout0);
counter s1 (en1 , clk , reset_n , dout1);
counter s2 (en2 , clk , reset_n , dout2);
'
'
'
counter s255 (en255 , clk , reset_n , dout255);

when simulating the test bench i am getting the error as Illegal output or inout port connection (port 'out1').