[SOLVED] Error: Subprogram <mmcm_count_calc> does not have a body when creating vhdl package.

LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.std_logic_unsigned.all;
  USE ieee.std_logic_misc.all;
  USE ieee.numeric_std.all;

package g1_mmcme2_drp_func_vhdl is

  function mmcm_count_calc (divide : std_logic_vector(7 downto 0) ; phase: std_logic_vector(31 downto 0) ; duty_cycle : integer) return std_logic_vector(37 downto 0);
            
end package  g1_mmcme2_drp_func_vhdl;

package body g1_mmcme2_drp_func_vhdl is
function mmcm_count_calc (
  divide     : in std_logic_vector(7 downto 0); -- Max divide is 128
  phase      : in std_logic_vector(31 downto 0);
  duty_cycle : integer)                         -- Multiplied by 100,000
  return std_logic_vector is 

  variable div_calc        : std_logic_vector(13 downto 0);
  variable phase_calc      : std_logic_vector(16 downto 0);
  begin
  
  div_calc   := mmcm_divider(divide, std_logic_vector(to_unsigned(duty_cycle,32)));
  -- mx[10:9], pm[8:6], dt[5:0]
  phase_calc(10 downto 0) := mmcm_phase(divide, phase);

  -- Return value is the upper and lower address of counter
  --    Upper address is:
  --       RESERVED    [31:26]
  --       MX          [25:24]
  --       EDGE        [23]
  --       NOCOUNT     [22]
  --       DELAY_TIME  [21:16]
  --    Lower Address is:
  --       PHASE_MUX   [15:13]
  --       RESERVED    [12]
  --       HIGH_TIME   [11:6]
  --       LOW_TIME    [5:0]

  return
        -- Upper Address
        "000000000000" & phase_calc(10 downto 9) & div_calc(13 downto 12) & phase_calc(5 downto 0) &
        -- Lower Address
        phase_calc(8 downto 6) & '0' & div_calc(11 downto 0);
 end function;
end g1_mmcme2_drp_func_vhdl;

LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.std_logic_unsigned.all;
  USE ieee.std_logic_misc.all;
  USE ieee.numeric_std.all;

package g1_mmcme2_drp_func_vhdl is

  type type_mmcm_count_calc is  
    record
      divide          : std_logic_vector(7 downto 0);  
      phase           : std_logic_vector(31 downto 0);  
      duty_cycle      : integer;   
  end record;

  function mmcm_count_calc (arguments: type_mmcm_count_calc) return std_logic_vector(37 downto 0);
            
end package  g1_mmcme2_drp_func_vhdl;

package body g1_mmcme2_drp_func_vhdl is

function mmcm_count_calc (
  arguments     : type_mmcm_count_calc)                         
  return std_logic_vector is 
  
  variable mmcm_count_calc : std_logic_vector(37 downto 0);
  variable div_calc        : std_logic_vector(13 downto 0);
  variable phase_calc      : std_logic_vector(16 downto 0);
  begin
  
  div_calc   := mmcm_divider(arguments.divide, std_logic_vector(to_unsigned(arguments.duty_cycle,32)));
  -- mx[10:9], pm[8:6], dt[5:0]
  phase_calc(10 downto 0) := mmcm_phase(arguments.divide, arguments.phase);

  -- Return value is the upper and lower address of counter
  --    Upper address is:
  --       RESERVED    [31:26]
  --       MX          [25:24]
  --       EDGE        [23]
  --       NOCOUNT     [22]
  --       DELAY_TIME  [21:16]
  --    Lower Address is:
  --       PHASE_MUX   [15:13]
  --       RESERVED    [12]
  --       HIGH_TIME   [11:6]
  --       LOW_TIME    [5:0]
  mmcm_count_calc := "000000000000" & phase_calc(10 downto 9) & div_calc(13 downto 12) & phase_calc(5 downto 0) &
          -- Lower Address
          phase_calc(8 downto 6) & '0' & div_calc(11 downto 0);
  return
  mmcm_count_calc;
        -- Upper Address
        
end function;
end g1_mmcme2_drp_func_vhdl;

BIBLIOTECA ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.std_logic_unsigned.all;
  USE ieee.std_logic_misc.all;
  USE ieee.numeric_std.all;

el paquete g1_mmcme2_drp_func_vhdl es

  función mmcm_count_calc (divide: std_logic_vector (7 downto 0); fase: std_logic_vector (31 downto 0); duty_cycle: integer) return std_logic_vector;
            
paquete final g1_mmcme2_drp_func_vhdl;

el cuerpo del paquete g1_mmcme2_drp_func_vhdl es
función mmcm_count_calc (
  dividir: en std_logic_vector (7 downto 0); - La división máxima es 128
  fase: en std_logic_vector (31 downto 0);
  duty_cycle: integer) - Multiplicado por 100,000
  return std_logic_vector es 

  variable div_calc: std_logic_vector (13 downto 0);
  variable phase_calc: std_logic_vector (16 downto 0);
  empezar
  
  div_calc: = mmcm_divider (divide, std_logic_vector (to_unsigned (duty_cycle, 32)));
  - mx [10: 9], pm [8: 6], dt [5: 0]
  phase_calc (10 downto 0): = mmcm_phase (división, fase);

  - El valor de retorno es la dirección superior e inferior del contador
  - La dirección superior es:
  - RESERVADO [31:26]
  - MX [25:24]
  - BORDE [23]
  - CUENTA [22]
  - DELAY_TIME [21:16]
  - Dirección inferior es:
  - PHASE_MUX [15:13]
  - RESERVADO [12]
  - HIGH_TIME [11: 6]
  - LOW_TIME [5: 0]

  regreso
        - Dirección superior
        "000000000000" y phase_calc (10 downto 9) y div_calc (13 downto 12) y phase_calc (5 downto 0) &
        - Dirección inferior
        phase_calc (8 downto 6) & '0' & div_calc (11 downto 0);
 función final;
end g1_mmcme2_drp_func_vhdl;

function mmcm_count_calc (arguments: type_mmcm_count_calc) return std_logic_vector[COLOR="#FF0000"](37 downto 0)[/COLOR];

función mmcm_count_calc (divide: std_logic_vector (7 downto 0); fase: std_logic_vector (31 downto 0); duty_cycle: integer) return std_logic_vector;