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[SOLVED] Error - section '.org_0' can not fit the absolute section. Section '.org_0' start=0x0

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J

jagdeepsingh3@hotmail.it

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hii all i want to update sine table of this code but when i build the asm file he gives me this error (Error - section '.org_0' can not fit the absolute section. Section '.org_0' start=0x00000000, length=0x00001002):sad: please help
Code: 
 LIST P=16F72, F=INHX8M
      include "P16F72.inc"
            

 __config _HS_OSC & _WDT_ON & _PWRTE_ON & _CP_OFF
W_TEMP equ 0x20	
BATTV equ 0x4D
AD_RESULT equ 0x33
SEL_CHANEL equ 0x32

goto init	
	nop
	nop
	nop
	goto isr	
	nop
	nop
	nop

table	    ADDWF   PCL , F
            RETLW   .0
            RETLW   .6
            RETLW   .13
            RETLW   .19
            RETLW   .25
            RETLW   .31
            RETLW   .37
            RETLW   .43
            RETLW   .49
            RETLW   .55
            RETLW   .60
            RETLW   .66
            RETLW   .71
            RETLW   .76
            RETLW   .81
            RETLW   .86
            RETLW   .91
            RETLW   .95
            RETLW   .99
            RETLW   .103
            RETLW   .106
            RETLW   .110
            RETLW   .113
            RETLW   .116
            RETLW   .118
            RETLW   .121
            RETLW   .122
            RETLW   .124
            RETLW   .126
            RETLW   .127
            RETLW   .127
            RETLW   .128
            RETLW   .128
            RETLW   .128
            RETLW   .127
            RETLW   .127
            RETLW   .126
            RETLW   .124
            RETLW   .122
            RETLW   .121
            RETLW   .118
            RETLW   .116
            RETLW   .113
            RETLW   .110
            RETLW   .106
            RETLW   .103
            RETLW   .99
            RETLW   .95
            RETLW   .91
            RETLW   .86
            RETLW   .81
            RETLW   .76
            RETLW   .71
            RETLW   .66
            RETLW   .60
            RETLW   .55
            RETLW   .49
            RETLW   .43
            RETLW   .37
            RETLW   .31
            RETLW   .25
            RETLW   .19
            RETLW   .13
            RETLW   .6
            RETLW   .0

   


init	clrf STATUS
	clrf PORTC
	clrf PORTB
	bcf STATUS,RP1
	bsf STATUS,RP0	; switch to bank 1
	movlw b'11000111'
	movwf OPTION_REG
	movlw b'111111' 
	movwf TRISA
	movlw b'00000100'
	movwf TRISC
	movlw b'00000111'
	movwf TRISB
	movlw .0
	movwf ADCON1
	bcf STATUS,RP0	; switch to bank 0
	movlw b'11000000'
	movwf INTCON
	movlw .0
	movwf 0x10
	bcf STATUS,RP0	; switch to bank 0
	movlw b'10000001'
	movwf ADCON0
	clrf PORTA
	movlw b'00000111'
	movwf PORTC
	call LEVEL_3	
	movlw .5
	movwf 0x3C
	movwf 0x2A
	movlw .10
	movwf 0x3E
	call LEVEL_4	
	call LEVEL_4
	goto LEVEL_5	

LEVEL_3	movlw .80
	movwf W_TEMP
	movlw .33
	movwf FSR
LEVEL_6	clrf INDF
	incf FSR,f
	decfsz W_TEMP,f
	goto LEVEL_6	
	return

ANASCAN	movlw .5
	movwf W_TEMP
LEVEL_7	decfsz W_TEMP,f
	goto LEVEL_7	
	movf SEL_CHANEL,w
	movwf W_TEMP
	bcf STATUS,C
	rlf W_TEMP,f
	rlf W_TEMP,f
	rlf W_TEMP,f
	movlw .129
	iorwf W_TEMP,w
	movwf ADCON0
	movlw .20
	movwf 0x37
LEVEL_10	decfsz 0x37,f
	goto LEVEL_8	
	goto LEVEL_9	
LEVEL_8	btfss 0x2C,0
	goto LEVEL_10	
	call LEVEL_11	
LEVEL_9	bsf ADCON0,2
LEVEL_12	btfsc 0x2C,0
	call LEVEL_11
	btfsc ADCON0,2
	goto LEVEL_12	
	movf ADRES,w
	movwf AD_RESULT
	bcf 0xC,6
	return

isr	bcf INTCON,GIE
	movwf 0x31
	movf STATUS,w
	movwf 0x30
	bcf 0xC,0
	bcf 0x10,0
	btfsc 0x2B,0
	goto LEVEL_13	
	btfsc 0x2C,3
	goto LEVEL_14	
	goto exit	

LEVEL_16	bcf PORTC,4
	bcf PORTC,5
	movf 0x26,w
	movwf TMR1L
	comf TMR1L,f
	movf 0x27,w
	movwf TMR1H
	comf TMR1H,f
	bsf PORTC,0
	bsf PORTC,1
	bsf 0x2D,5
	bsf 0x10,0
	goto exit

LEVEL_14	btfss 0x2D,5
	goto LEVEL_16	
	bcf PORTC,4
	bcf PORTC,5
	movf 0x28,w
	movwf 0x26
	movf 0x29,w
	movwf 0x27
	movf 0x24,w
	movwf 0x22
	movwf TMR1L
	comf TMR1L,f
	movf 0x25,w
	movwf 0x23
	movwf TMR1H
	comf TMR1H,f
	bcf PORTC,0
	bcf PORTC,1
	bcf 0x2D,5
	bsf 0x10,0
	goto exit

LEVEL_13	btfss 0x2D,5
	goto LEVEL_17	
	bcf 0x2D,5
	bsf 0x2C,0
	movf 0x28,w
	movwf 0x26
	movf 0x29,w
	movwf 0x27
	movf 0x24,w
	movwf 0x22
	movwf TMR1L
	comf TMR1L,f
	movf 0x25,w
	movwf 0x23
	movwf TMR1H
	comf TMR1H,f
	movf 0x21,w
	btfss STATUS,Z
	goto LEVEL_18	
	movlw .8
	xorwf 0x2B,f
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

;DEAD BAND


;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
LEVEL_18	bsf 0x10,0
	btfsc 0x2B,3
	goto LEVEL_19	
	bcf PORTC,5
	bsf PORTC,0
	nop
	nop
	nop
	nop
	nop
	bsf PORTC,4
	bcf PORTC,1
	goto exit

LEVEL_19	bcf PORTC,4
	bsf PORTC,1
	nop
	nop
	nop
	nop
	nop
	bsf PORTC,5
	bcf PORTC,0
	goto exit
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

;DEAD BAND

;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
LEVEL_17	bcf PORTC,4
	bcf PORTC,5
	movf 0x26,w
	movwf TMR1L
	comf TMR1L,f
	movf 0x27,w
	movwf TMR1H
	comf TMR1H,f
	bcf PORTC,0
	bcf PORTC,1
	bsf 0x2D,5
	bsf 0x10,0

exit	movf 0x30,w
	movwf STATUS
	movf 0x31,w
	bsf INTCON,GIE
	retfie


LEVEL_42	movlw .2                  ;MAINS SENCE
	movwf SEL_CHANEL
	call ANASCAN	                  ;LEVEL 21,22,23
	movf AD_RESULT,w
	sublw .67
	btfsc STATUS,C
	goto LEVEL_21	
	movf AD_RESULT,w
	sublw .138
	btfss STATUS,C
	goto LEVEL_21
	movf AD_RESULT,w
	sublw .68
	btfsc STATUS,C
	goto LEVEL_22	
	movf AD_RESULT,w
	sublw .135
	btfsc STATUS,C
	goto LEVEL_23	
LEVEL_22	clrf 0x55
	clrf 0x34
	clrf 0x35
	return


LEVEL_23	btfsc 0x2B,1
	return
	clrf 0x55
	movlw .4
	movwf 0x3D
	movlw .1
	addwf 0x34,f
	btfss STATUS,C
	return
	incf 0x35,f
	movf 0x35,w
	sublw .50
	btfsc STATUS,C
	return
	clrf 0x34
	clrf 0x35
	goto LEVEL_24	
LEVEL_21	btfsc 0x2B,0
	return
	incf 0x55,f
	clrf 0x34
	clrf 0x35
	movf 0x55,w
	sublw .15
	btfsc STATUS,C
	return
	goto LEVEL_25	
LEVEL_40	btfss 0xC,2
	goto LEVEL_26	
	bcf 0xC,2
	clrf 0x36
	goto LEVEL_27	
LEVEL_26	btfss 0x2C,6
	return
	incf 0x36,f
	movlw .4
	subwf 0x36,w
	btfss STATUS,C
	return
	clrf 0x36
LEVEL_25	btfss 0x2C,7
	goto LEVEL_28	
	btfsc 0x2B,0
	return
LEVEL_76	btfsc 0x2D,3
	return
	call LEVEL_29	
	movlw .7
	movwf 0x38
	call LEVEL_30	
	bsf PORTC,7
	call LEVEL_4
	call LEVEL_4
	clrf 0x34
	clrf 0x35
	clrf 0x55
	call LEVEL_31	
	bcf 0x2B,1
	bcf PORTB,4
	bcf PORTB,5
	bcf 0x2D,3
	bcf PORTB,7
	movlw .10
	movwf 0x3D
	bsf 0x2B,0
	movlw .0
	movwf 0x21
	call LEVEL_11
	bsf 0x2D,5
	movlw .200
	movwf TMR1L
	movlw .255
	movwf TMR1H
	bsf STATUS,RP0	; switch to bank 1
	bsf 0x8C,0
	bcf STATUS,RP0	; switch to bank 0
	bsf 0x10,0
	bsf INTCON,GIE
	clrf 0x40
	clrf 0x41
	clrf 0x42
	clrf 0x4C
	return

LEVEL_28	btfss 0x2C,3
	goto LEVEL_32	
	call LEVEL_29
	call LEVEL_31
LEVEL_32	clrf 0x55
	bcf 0x2B,1
	bcf PORTB,4
	return

LEVEL_27	btfsc 0x2B,1
	return
	movlw .1
	addwf 0x34,f
	btfss STATUS,C
	return
	incf 0x35,f
	movlw .10
	movwf 0x3D
	movf 0x35,w
	sublw .2
	btfsc STATUS,C
	return
	clrf 0x34
	clrf 0x35
LEVEL_24	call LEVEL_33	
	bsf 0x2B,1
	bsf PORTB,4
LEVEL_31	bcf PORTB,6
	bcf 0x2C,3
	movlw .100
	movwf 0x54
	movlw .50
	movwf 0x2F
	return
LEVEL_33	call LEVEL_29
	call LEVEL_4
	clrf 0x2E
	clrf 0x3A
	clrf 0x3B
	bcf 0x2B,0
	bcf 0x2D,3
	bcf PORTB,7
	bcf PORTB,5
	bcf PORTC,7
	call LEVEL_4
	return
LEVEL_4	clrwdt
	movlw .25
	movwf 0x38
LEVEL_30	clrwdt
	movlw .0
	movwf W_TEMP
LEVEL_34	clrwdt
	decfsz W_TEMP,f
	goto LEVEL_34	
	decfsz 0x38,f
	goto LEVEL_30
	return
LEVEL_54	movlw .1   ; BATTERY SENCE
	movwf SEL_CHANEL
	call ANASCAN
	movf AD_RESULT,w
	addwf 0x43,f
	btfss STATUS,C
	goto LEVEL_35	
	movf 0x44,w
	addlw .1
	movwf 0x44
LEVEL_35	movf 0x45,w
	addlw .1
	movwf 0x45
	andlw .128
	btfsc STATUS,Z
	goto LEVEL_36	
	call LEVEL_37	
	movf BATTV,w
	sublw .215      ;CHG CUT OFF
	btfsc STATUS,C
	goto LEVEL_36
	call LEVEL_29
	call LEVEL_31
LEVEL_36	goto LEVEL_38	
LEVEL_29	bcf INTCON,GIE
	bcf 0x10,0
	bcf 0x12,2
	bcf 0xC,0
	bcf 0xC,2
	bsf STATUS,RP0	; switch to bank 1
	bcf 0x8C,0
	bcf STATUS,RP0	; switch to bank 0
	bcf PORTC,4
	bcf PORTC,5
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	bsf PORTC,0
	bsf PORTC,1
	return
LEVEL_5	movlw .0
	movwf TMR0
	movlw .4
	movwf 0x17
	clrf 0x3A
	clrf 0x3B
	clrf 0x2E
	movlw .10
	movwf 0x39
	movlw .100
	movwf 0x54
	movlw .10
	movwf 0x3E
	clrf 0x34
	clrf 0x35
	clrf 0x55
	movlw .25
	movwf 0x2A
	movlw .50
	movwf 0x2F
	bcf 0x2C,7
	bcf 0xC,2
	movlw .10
	movwf 0x3D
	bcf PORTC,7
	call LEVEL_4
	call LEVEL_4
	call LEVEL_4
LEVEL_38	clrwdt
	bcf 0x2C,6
	btfsc INTCON,T0IF
	bsf 0x2C,6
	bcf INTCON,T0IF
	btfsc 0x2C,0
	call LEVEL_11
	btfsc PORTA,4
	goto LEVEL_39	
	call LEVEL_40	
	goto LEVEL_41	
LEVEL_39	call LEVEL_42	
LEVEL_41	call LEVEL_43	
	btfsc 0x2B,1
	goto LEVEL_44	
	goto LEVEL_45	
LEVEL_45	btfss 0x2B,0
	goto LEVEL_46	
	btfsc 0x2C,7
	goto LEVEL_47	
	call LEVEL_33
	goto LEVEL_46
LEVEL_47	movf 0x2E,w
	btfss STATUS,Z
	goto LEVEL_46
	movlw .4                   ;OVERLOAD SENCE
	movwf SEL_CHANEL
	call ANASCAN
	movf AD_RESULT,w
	sublw .120
	btfss STATUS,C
	goto LEVEL_48	
	movf AD_RESULT,w
	sublw .60
	btfsc STATUS,C
	goto LEVEL_49	
	movlw .10
	movwf 0x3D
	movlw .1
	addwf 0x3A,f
	btfss STATUS,C
	goto LEVEL_49
	incf 0x3B,f
	movf 0x3B,w
	sublw .5
	btfsc STATUS,C
	goto LEVEL_49
LEVEL_48	call LEVEL_29
	clrf 0x3A
	clrf 0x3B
	movlw .50
	movwf 0x2E
	movlw .50
	movwf 0x3D
	bsf PORTB,5
	goto LEVEL_46
LEVEL_49	bcf PORTB,5
	movf BATTV,w
	btfsc STATUS,Z
	goto LEVEL_50	
	bcf 0x2D,3            
	sublw .154           ;LOW BATTERY BEEP
	btfss STATUS,C
	goto LEVEL_50
	bsf 0x2D,3            
	movf BATTV,w
	sublw .148        ;LOW BATTERY CUT 
	btfss STATUS,C
	goto LEVEL_50
	call LEVEL_29
	bsf 0x2D,3
	goto LEVEL_46
LEVEL_50	movlw .0          ;FEED BACK
	movwf SEL_CHANEL
	call ANASCAN
	movf AD_RESULT,w
	addwf 0x40,f
	btfss STATUS,C
	goto LEVEL_51	
	movf 0x41,w
	addlw .1	
	movwf 0x41
LEVEL_51	movf 0x42,w
	addlw .1	
	movwf 0x42
	andlw b'00100000'
	btfsc STATUS,Z
	goto LEVEL_46
	call LEVEL_52	
	call LEVEL_53	
LEVEL_46	goto LEVEL_54	
LEVEL_44	btfss 0x2B,1
	goto LEVEL_55	
	btfsc 0x2C,3
	goto LEVEL_56	
	movf BATTV,w
	sublw .201              ;CHG RESTART
	btfss STATUS,C
	goto LEVEL_55
	movf 0x2F,w
	btfss STATUS,Z
	goto LEVEL_55
	bsf 0x2C,3
	bsf PORTB,4
	bsf PORTB,6
	clrf 0x46
	clrf 0x47
	clrf 0x48
	clrf 0x4E
	movlw .100
	movwf 0x54
	call LEVEL_57	; LEVEL_57 = 0x346
	movlw .200
	movwf TMR1L
	movlw .255
	movwf TMR1H
	bsf 0x2D,5
	bsf STATUS,RP0	; switch to bank 1
	bsf 0x8C,0
	bcf STATUS,RP0	; switch to bank 0
	bsf 0x10,0
	bsf INTCON,GIE
	goto LEVEL_55
LEVEL_56	movlw .3     ;CHARGING CURRENT 
	movwf SEL_CHANEL
	call ANASCAN
	movf AD_RESULT,w
	sublw .180
	btfsc STATUS,C
	goto LEVEL_58	
	call LEVEL_29
	call LEVEL_31
	goto LEVEL_55
LEVEL_58	movf AD_RESULT,w
	addwf 0x46,f
	btfss STATUS,C
	goto LEVEL_59	
	movf 0x47,w
	addlw .1
	movwf 0x47
LEVEL_59	movf 0x48,w
	addlw .1
	movwf 0x48
	andlw .32
	btfsc STATUS,Z
	goto LEVEL_55
	call LEVEL_60	
	call LEVEL_61	
LEVEL_55	goto LEVEL_54
LEVEL_52	movlw .5
	movwf W_TEMP
LEVEL_62	bcf STATUS,C
	rrf 0x41,f
	rrf 0x40,f
	decfsz W_TEMP,f
	goto LEVEL_62	
	movf 0x40,w
	movwf 0x4C
	clrf 0x40
	clrf 0x41
	clrf 0x42
	return
LEVEL_37	movlw .7
	movwf W_TEMP
LEVEL_63	bcf STATUS,C
	rrf 0x44,f
	rrf 0x43,f
	decfsz W_TEMP,f
	goto LEVEL_63	
	movf 0x43,w
	movwf BATTV
	clrf 0x43
	clrf 0x44
	clrf 0x45
	return
LEVEL_60	movlw .5
	movwf W_TEMP
LEVEL_64	bcf STATUS,C
	rrf 0x47,f
	rrf 0x46,f
	decfsz W_TEMP,f
	goto LEVEL_64	
	movf 0x46,w
	movwf 0x4E
	clrf 0x46
	clrf 0x47
	clrf 0x48
	return
LEVEL_43	btfss 0x2C,6
	goto LEVEL_65	
	btfss 0x2C,3
	goto LEVEL_66	
	btfsc 0x2C,5
	goto LEVEL_66
	movlw .128
	subwf 0x54,w
	btfsc STATUS,C
	goto LEVEL_67	
	incf 0x54,f
	goto LEVEL_67
LEVEL_66	btfss 0x2B,0
	goto LEVEL_67
	btfsc 0x2B,7
	goto LEVEL_67
	movlw .128
	subwf 0x39,w
	btfsc STATUS,C
	goto LEVEL_67
	incf 0x39,f
LEVEL_67	btfsc PORTB,2
	goto LEVEL_68	
	movf 0x2A,w
	btfsc STATUS,Z
	goto LEVEL_69	
	decfsz 0x2A,f
	goto LEVEL_70	
	btfsc 0x2B,5
	goto LEVEL_69
	bsf 0x2B,5
	btfsc 0x2C,7
	goto LEVEL_71	
	bsf 0x2C,7
	bsf PORTB,3
	movlw .10
	movwf 0x3D
	goto LEVEL_70
LEVEL_71	bcf 0x2C,7
	bcf PORTB,3
	movlw .10
	movwf 0x3D
	btfsc 0x2B,0
	call LEVEL_33
	movlw .10
	movwf 0x39
	movlw .10
	movwf 0x3E
	goto LEVEL_70
LEVEL_68	bcf 0x2B,5
LEVEL_69	movlw .30
	movwf 0x2A
LEVEL_70	decfsz 0x3C,f
	goto LEVEL_65
	movlw .20
	movwf 0x3C
	btfss 0x2D,3
	goto LEVEL_72	
	movlw .10
	movwf 0x3D
	movlw .128
	xorwf PORTB,f
LEVEL_72	btfss 0x2B,1
	goto LEVEL_73	
	btfss 0x2C,3
	goto LEVEL_74	
	movlw .64
	xorwf PORTB,f
LEVEL_74	movf 0x2F,w
	btfss STATUS,Z
	decf 0x2F,f
LEVEL_73	btfss 0x2B,0
	goto LEVEL_75	
	movf 0x2E,w
	btfsc STATUS,Z
	goto LEVEL_75
	decfsz 0x2E,f
	goto LEVEL_75
	movlw .10
	movwf 0x39
	movlw .10
	movwf 0x3E
	call LEVEL_76	
LEVEL_75	movf 0x3D,w
	btfsc STATUS,Z
	goto LEVEL_65
	movlw b'1000000' 
	xorwf PORTC,f
	decfsz 0x3D,f
	goto LEVEL_65
	bcf PORTC,6
LEVEL_65	return
LEVEL_61	movf 0x4E,w
	sublw .5
	btfsc STATUS,C
	goto LEVEL_57
	bcf 0x2C,5
	movf 0x4E,w
	subwf 0x54,w
	movwf 0x52
	btfss STATUS,C
	goto LEVEL_77	
	sublw .2
	btfss STATUS,C
	goto LEVEL_78	
	return

LEVEL_78	bcf STATUS,C
	rrf 0x52,f
	clrf 0x53
	movlw .1
	movwf 0x52
	movf 0x24,w
	addwf 0x52,f
	btfsc STATUS,C
	incf 0x53,f
	movf 0x25,w
	addwf 0x53,f
	movf 0x52,w
	sublw .0
	movf 0x53,w
	movwf W_TEMP
	btfss STATUS,C
	incf W_TEMP,f
	movf W_TEMP,w
	sublw .2
	btfsc STATUS,C
	goto LEVEL_79	
	movlw .0	
	movwf 0x24
	movlw .2	
	movwf 0x25
	goto LEVEL_80	
LEVEL_79	movf 0x52,w
	movwf 0x24
	movf 0x53,w
	movwf 0x25
	goto LEVEL_80
LEVEL_77	comf 0x52,f
	incf 0x52,f
	movf 0x52,w
	sublw .2
	btfsc STATUS,C
	return
	bcf STATUS,C
	rrf 0x52,f
	clrf 0x53
	movlw .5
	movwf 0x52
	movf 0x52,w
	subwf 0x24,f
	movwf 0x52
	btfss STATUS,C
	incf 0x53,f
	movf 0x53,w
	subwf 0x25,f
	movwf 0x53
	btfsc STATUS,C
	goto LEVEL_80
LEVEL_57	bsf 0x2C,5
	movlw .20
	movwf 0x24
	movlw .0
	movwf 0x25
LEVEL_80	bcf STATUS,C
	movf 0x25,w
	movwf W_TEMP
	movf 0x24,w
	sublw .200
	movwf 0x28
	btfss STATUS,C
	incf W_TEMP,f
	movf W_TEMP,w
	sublw .2
	movwf 0x29
	return

LEVEL_53	movf 0x4C,w
	sublw .5
	btfsc STATUS,C
	goto LEVEL_81	
	bcf 0x2B,7
	bcf 0x2B,2
	movf 0x4C,w
	subwf 0x39,w
	movwf 0x52
	btfsc STATUS,C
	goto LEVEL_82	
	bsf 0x2B,2
	comf 0x52,f
	incf 0x52,f
LEVEL_82	movf 0x52,w
	sublw .2
	btfss STATUS,C
	goto LEVEL_83	
	return

LEVEL_83	bcf STATUS,C
	rrf 0x52,f
	rrf 0x52,f
	movlw .1
	movwf 0x52
	btfss 0x2B,2
	goto LEVEL_84	
	movf 0x52,w
	subwf 0x3E,f
	movf 0x3E,w
	sublw .89
	btfss STATUS,C
	goto LEVEL_85	
	return

LEVEL_84	movf 0x52,w
	addwf 0x3E,f
	movf 0x3E,w
	sublw .89
	btfsc STATUS,C
	return
	movlw .89
	movwf 0x3E
	return

LEVEL_81	bsf 0x2B,7
	movlw .10
	movwf 0x39

LEVEL_85	movlw .10
	movwf 0x3E
	return

LEVEL_11	bcf 0x2C,0
	incf 0x21,f
	btfss 0x21,6
	goto LEVEL_86	
	clrf 0x21

LEVEL_86	movf 0x21,w
	call table	
	movwf 0x50
	movf 0x3E,w
	movwf 0x51
	call LEVEL_88	
	bcf STATUS,C
	rrf 0x53,f
	rrf 0x52,f
	bcf STATUS,C
	rrf 0x53,f
	rrf 0x52,f
	bcf STATUS,C
	rrf 0x53,f
	rrf 0x52,f
	bcf STATUS,C
	rrf 0x53,f
	rrf 0x52,f
	movf 0x52,w
	movwf 0x24
	movf 0x53,w
	movwf 0x25
	bcf STATUS,C
	movf 0x24,w
	sublw .200
	movwf 0x28
	movf 0x25,w
	movwf W_TEMP
	btfss STATUS,C
	incf W_TEMP,f
	movf W_TEMP,w
	sublw .2
	movwf 0x29
	return

LEVEL_88	clrf 0x53
	clrf 0x52
	movf 0x50,w
	bcf STATUS,C
	btfsc 0x51,0
	addwf 0x53,f
	rrf 0x53,f
	rrf 0x52,f
	btfsc 0x51,1
	addwf 0x53,f
	rrf 0x53,f
	rrf 0x52,f
	btfsc 0x51,2
	addwf 0x53,f
	rrf 0x53,f
	rrf 0x52,f
	btfsc 0x51,3
	addwf 0x53,f
	rrf 0x53,f
	rrf 0x52,f
	btfsc 0x51,4
	addwf 0x53,f
	rrf 0x53,f
	rrf 0x52,f
	btfsc 0x51,5
	addwf 0x53,f
	rrf 0x53,f
	rrf 0x52,f
	btfsc 0x51,6
	addwf 0x53,f
	rrf 0x53,f
	rrf 0x52,f
	btfsc 0x51,7
	addwf 0x53,f
	rrf 0x53,f
	rrf 0x52,f
	retlw .0
	addlw .166
	addlw .255
	addlw .255
	addlw .255
	addlw .255
	movlw .10
	addwf 0x52,f
	btfsc STATUS,C
	incf 0x53,f
	movlw .8
	addwf 0x53,f
	movf 0x53,w
	movwf PCLATH
	movf 0x52,w
	movwf PCL
	retlw .0	
	retlw .0
	retlw .0	
	retlw .0	
	retlw .227
	retlw .54
	retlw .0
	retlw .227
	retlw .62
	retlw .0
	retlw .228
	retlw .8	
	retlw .0	
	retlw .228
	retlw .20
	retlw .0
	retlw .228
	retlw .34
	retlw .0
	retlw .228
	retlw .54
	retlw .0	
	retlw .229
	retlw .32
	retlw .0
	retlw .230
	retlw .48
	retlw .0
	retlw .231
	retlw .16
	retlw .0
	retlw .231
	retlw .44
	retlw .0	
	retlw .232
	retlw .4	
	retlw .0	
	retlw .232
	retlw .54
	retlw .0
	retlw .233
	retlw .6	
	retlw .0	
	retlw .233
	retlw .60
	retlw .0
	retlw .234
	retlw .27
	retlw .0
	retlw .234
	retlw .36
	retlw .0
	retlw .227
	retlw .57
	retlw .0	
	retlw .228
	retlw .17
	retlw .0
	retlw .228
	retlw .41
	retlw .0
	retlw .229
	retlw .1
	retlw .0
	retlw .229
	retlw .25
	retlw .0
	retlw .229
	retlw .49
	retlw .0
	retlw .230
	retlw .9
	retlw .0
	retlw .230
	retlw .33
	retlw .0
	retlw .230
	retlw .57
	retlw .0
	retlw .231
	retlw .17
	retlw .0
	retlw .231
	retlw .41
	retlw .0
	retlw .232
	retlw .1
	retlw .0
	retlw .232
	retlw .25
	retlw .0
	retlw .232
	retlw .49
	retlw .0
	retlw .233
	retlw .9
	retlw .0
	retlw .233
	retlw .33
	retlw .0
	retlw .227
	retlw .60
	retlw .0
	retlw .228
	retlw .21
	retlw .0
	retlw .228
	retlw .44
	retlw .0
	retlw .229
	retlw .4
	retlw .0
	retlw .229
	retlw .28
	retlw .0
	retlw .229
	retlw .52
	retlw .0
	retlw .230
	retlw .12
	retlw .0
	retlw .230
	retlw .36
	retlw .0
	retlw .230
	retlw .60
	retlw .0
	retlw .231
	retlw .20
	retlw .0
	retlw .231
	retlw .45
	retlw .0
	retlw .232
	retlw .5
	retlw .0
	retlw .232
	retlw .28
	retlw .0	
	retlw .232
	retlw .52
	retlw .0
	retlw .233
	retlw .12
	retlw .0
	retlw .233
	retlw .36
	retlw .0
	retlw .227
	retlw .63
	retlw .0
	retlw .228
	retlw .23
	retlw .0
	retlw .228
	retlw .47
	retlw .0
	retlw .229
	retlw .7
	retlw .0
	retlw .229
	retlw .31
	retlw .0	
	retlw .229
	retlw .55
	retlw .0
	retlw .230
	retlw .15
	retlw .0	
	retlw .230
	retlw .39
	retlw .0
	retlw .230
	retlw .63
	retlw .0
	retlw .231
	retlw .23
	retlw .0
	retlw .231
	retlw .47
	retlw .0
	retlw .232
	retlw .7
	retlw .0
	retlw .232
	retlw .31
	retlw .0
	retlw .232
	retlw .55
	retlw .0
	retlw .233
	retlw .15
	retlw .0
	retlw .233
	retlw .39
	retlw .0
	retlw .228
	retlw .2
	retlw .0
	retlw .228
	retlw .26
	retlw .0	
	retlw .228
	retlw .50
	retlw .0
	retlw .229
	retlw .10
	retlw .0
	retlw .229
	retlw .34
	retlw .0
	retlw .229
	retlw .58
	retlw .0
	retlw .230
	retlw .18
	retlw .0	
	retlw .230
	retlw .42
	retlw .0
	retlw .231
	retlw .2
	retlw .0
	retlw .231
	retlw .26
	retlw .0
	retlw .231
	retlw .50
	retlw .0
	retlw .232
	retlw .10
	retlw .0
	retlw .232
	retlw .34
	retlw .0
	retlw .232
	retlw .58
	retlw .0
	retlw .233
	retlw .18
	retlw .0
	retlw .233
	retlw .42
	retlw .0	
	retlw .228
	retlw .5
	retlw .0
	retlw .228
	retlw .29
	retlw .0
	retlw .228
	retlw .53
	retlw .0
	retlw .229
	retlw .13
	retlw .0
	retlw .229
	retlw .37
	retlw .0
	retlw .229
	retlw .61
	retlw .0
	retlw .230
	retlw .21
	retlw .0
	retlw .230
	retlw .45
	retlw .0
	retlw .231
	retlw .5
	retlw .0
	retlw .231
	retlw .29
	retlw .0
	retlw .231
	retlw .53
	retlw .0
	retlw .232
	retlw .13
	retlw .0
	retlw .232
	retlw .37
	retlw .0
	retlw .232
	retlw .61
	retlw .0
	retlw .233
	retlw .21
	retlw .0
	retlw .233
	retlw .45
	retlw .0
	retlw .228
	retlw .9
	retlw .0	
	retlw .228
	retlw .32
	retlw .0
	retlw .228
	retlw .56
	retlw .0
	retlw .229
	retlw .16
	retlw .0
	retlw .229
	retlw .40
	retlw .0
	retlw .230
	retlw .0
	retlw .0
	retlw .230
	retlw .24
	retlw .0	
	retlw .230
	retlw .31
	retlw .0
	retlw .231
	retlw .8
	retlw .0
	retlw .231
	retlw .32
	retlw .0
	retlw .231
	retlw .56
	retlw .0
	retlw .232
	retlw .16
	retlw .0
	retlw .232
	retlw .40
	retlw .0
	retlw .233
	retlw .0
	retlw .0
	retlw .233
	retlw .24
	retlw .0
	retlw .233
	retlw .48
	retlw .0
	retlw .228
	retlw .11
	retlw .0
	retlw .228
	retlw .35
	retlw .0
	retlw .228
	retlw .59
	retlw .0
	retlw .229
	retlw .19
	retlw .0
	retlw .229
	retlw .43
	retlw .0
	retlw .230
	retlw .3
	retlw .0
	retlw .230
	retlw .27
	retlw .0
	retlw .230
	retlw .51
	retlw .0
	retlw .231
	retlw .11
	retlw .0
	retlw .231
	retlw .35
	retlw .0
	retlw .231
	retlw .59
	retlw .0
	retlw .232
	retlw .19
	retlw .0
	retlw .232
	retlw .43
	retlw .0
	retlw .233
	retlw .3
	retlw .0
	retlw .233
	retlw .27
	retlw .0
	retlw .233
	retlw .51
	retlw .0
	retlw .228
	retlw .14
	retlw .0
	retlw .228
	retlw .38
	retlw .0
	retlw .228
	retlw .62
	retlw .0
	retlw .229
	retlw .22
	retlw .0
	retlw .229
	retlw .46
	retlw .0
	retlw .230
	retlw .6
	retlw .0
	retlw .230
	retlw .30
	retlw .0
	retlw .230
	retlw .54
	retlw .0
	retlw .231
	retlw .14
	retlw .0
	retlw .231
	retlw .38
	retlw .0
	retlw .231
	retlw .62
	retlw .0
	retlw .232
	retlw .22
	retlw .0
	retlw .232
	retlw .46
	retlw .0
	retlw .233
	retlw .7
	retlw .0
	retlw .233
	retlw .30
	retlw .0
	retlw .233
	retlw .54
	movlw .199
	addwf 0x52,f
	btfsc STATUS,C
	incf 0x53,f
	movlw .9
	addwf 0x53,f
	movf 0x53,w
	movwf PCLATH
	movf 0x52,w
	movwf PCL
	retlw .0	
	retlw .0	
	retlw .0
	retlw .0	
	retlw .0	
	retlw .0	
	retlw .8	
	retlw .0	
	retlw .0	
	retlw .1
	retlw .0
	retlw .0
	retlw .8	
	retlw .0
	retlw .0
	retlw .5
	retlw .0
	retlw .0
	retlw .8
	retlw .0	
	retlw .1
	retlw .0
	retlw .0	
	retlw .0
	retlw .8	
	retlw .0	
	retlw .1	
	retlw .6	
	retlw .0	
	retlw .0	
	retlw .8	
	retlw .0	
	retlw .2
	retlw .3	
	retlw .0
	retlw .0
	retlw .8	
	retlw .0	
	retlw .3	
	retlw .3	
	retlw .0	
	retlw .0	
	retlw .8	
	retlw .0	
	retlw .5	
	retlw .4	
	retlw .0
	retlw .0
	retlw .8	
	retlw .0	
	retlw .9	
	retlw .4
	retlw .0	
	retlw .0
	retlw .8	
	retlw .1	
	retlw .1
	retlw .0
	retlw .0	
	retlw .0	
	retlw .8	
	retlw .1	
	retlw .2
	retlw .4	
	retlw .0	
	retlw .0	
	retlw .8
	retlw .1	
	retlw .3	
	retlw .6
	retlw .0	
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .9	; d'9' b'1001' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .9	; d'9' b'1001' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .3	; d'3' b'11' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .9	; d'9' b'1001' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .3	; d'3' b'11' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .3	; d'3' b'11' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .9	; d'9' b'1001' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .3	; d'3' b'11' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .9	; d'9' b'1001' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .3	; d'3' b'11' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .3	; d'3' b'11' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .9	; d'9' b'1001' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .3	; d'3' b'11' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .9	; d'9' b'1001' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .3	; d'3' b'11' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .3	; d'3' b'11' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .9	; d'9' b'1001' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .9	; d'9' b'1001' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .3	; d'3' b'11' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .3	; d'3' b'11' a'¶'
	retlw .9	; d'9' b'1001' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .3	; d'3' b'11' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .3	; d'3' b'11' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .9	; d'9' b'1001' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .2	; d'2' b'10' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .4	; d'4' b'100' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .7	; d'7' b'111' a'¶'
	retlw .6	; d'6' b'110' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .1	; d'1' b'1' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .5	; d'5' b'101' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .8	; d'8' b'1000' a'¶'
	retlw .0	; d'0' b'0' a'¶'
	retlw .2
	retlw .2
	retlw .0
	retlw .0
	retlw .8
	retlw .0
	retlw .3
	retlw .4
	retlw .0
	retlw .0
	retlw .8
	retlw .0
	retlw .4
	retlw .6
	retlw .0
	retlw .0
	retlw .8
	retlw .0
	retlw .5
    end

Code: 
Debug build of project `C:\Users\jagdeep\Downloads\pic16f72_sine_wave_ups_with_source_code_and_schematic_1585\New folder\ll.mcp' started.
Language tool versions: MPASMWIN.exe v5.44, mplink.exe v4.42, mplib.exe v4.42
Preprocessor symbol `__DEBUG' is defined.
Wed Apr 03 21:38:45 2013
----------------------------------------------------------------------
Make: The target "C:\Users\jagdeep\Downloads\pic16f72_sine_wave_ups_with_source_code_and_schematic_1585\pic16f72 sine wave ups with source code and schematic\16f72.o" is out of date.
Executing: "C:\Program Files\Microchip\MPASM Suite\MPASMWIN.exe" /q /p16F72 "16f72.asm" /l"16f72.lst" /e"16f72.err" /d__DEBUG=1
Warning[203] C:\USERS\JAGDEEP\DOWNLOADS\PIC16F72_SINE_WAVE_UPS_WITH_SOURCE_CODE_AND_SCHEMATIC_1585\PIC16F72 SINE WAVE UPS WITH SOURCE CODE AND SCHEMATIC\16F72.ASM 12 : Found opcode in column 1. (goto)
Message[302] C:\USERS\JAGDEEP\DOWNLOADS\PIC16F72_SINE_WAVE_UPS_WITH_SOURCE_CODE_AND_SCHEMATIC_1585\PIC16F72 SINE WAVE UPS WITH SOURCE CODE AND SCHEMATIC\16F72.ASM 98 : Register in operand not in bank 0.  Ensure that bank bits are correct.
Message[302] C:\USERS\JAGDEEP\DOWNLOADS\PIC16F72_SINE_WAVE_UPS_WITH_SOURCE_CODE_AND_SCHEMATIC_1585\PIC16F72 SINE WAVE UPS WITH SOURCE CODE AND SCHEMATIC\16F72.ASM 100 : Register in operand not in bank 0.  Ensure that bank bits are correct.
Message[302] C:\USERS\JAGDEEP\DOWNLOADS\PIC16F72_SINE_WAVE_UPS_WITH_SOURCE_CODE_AND_SCHEMATIC_1585\PIC16F72 SINE WAVE UPS WITH SOURCE CODE AND SCHEMATIC\16F72.ASM 102 : Register in operand not in bank 0.  Ensure that bank bits are correct.
Message[302] C:\USERS\JAGDEEP\DOWNLOADS\PIC16F72_SINE_WAVE_UPS_WITH_SOURCE_CODE_AND_SCHEMATIC_1585\PIC16F72 SINE WAVE UPS WITH SOURCE CODE AND SCHEMATIC\16F72.ASM 104 : Register in operand not in bank 0.  Ensure that bank bits are correct.
Message[302] C:\USERS\JAGDEEP\DOWNLOADS\PIC16F72_SINE_WAVE_UPS_WITH_SOURCE_CODE_AND_SCHEMATIC_1585\PIC16F72 SINE WAVE UPS WITH SOURCE CODE AND SCHEMATIC\16F72.ASM 106 : Register in operand not in bank 0.  Ensure that bank bits are correct.
Message[302] C:\USERS\JAGDEEP\DOWNLOADS\PIC16F72_SINE_WAVE_UPS_WITH_SOURCE_CODE_AND_SCHEMATIC_1585\PIC16F72 SINE WAVE UPS WITH SOURCE CODE AND SCHEMATIC\16F72.ASM 392 : Register in operand not in bank 0.  Ensure that bank bits are correct.
Message[302] C:\USERS\JAGDEEP\DOWNLOADS\PIC16F72_SINE_WAVE_UPS_WITH_SOURCE_CODE_AND_SCHEMATIC_1585\PIC16F72 SINE WAVE UPS WITH SOURCE CODE AND SCHEMATIC\16F72.ASM 490 : Register in operand not in bank 0.  Ensure that bank bits are correct.
Message[302] C:\USERS\JAGDEEP\DOWNLOADS\PIC16F72_SINE_WAVE_UPS_WITH_SOURCE_CODE_AND_SCHEMATIC_1585\PIC16F72 SINE WAVE UPS WITH SOURCE CODE AND SCHEMATIC\16F72.ASM 653 : Register in operand not in bank 0.  Ensure that bank bits are correct.
Make: The target "C:\Users\jagdeep\Downloads\pic16f72_sine_wave_ups_with_source_code_and_schematic_1585\New folder\16f72.cof" is out of date.
Executing: "C:\Program Files\Microchip\MPASM Suite\mplink.exe" /p16F72 "..\pic16f72 sine wave ups with source code and schematic\16f72.o" /u_DEBUG /z__MPLAB_BUILD=1 /z__MPLAB_DEBUG=1 /o"16f72.cof" /M"16f72.map" /W /x
MPLINK 4.42, Linker
Device Database Version 1.7
Copyright (c) 1998-2011 Microchip Technology Inc.
Error - section '.org_0' can not fit the absolute section. Section '.org_0' start=0x00000000, length=0x00001002
Errors    : 1

Link step failed.
----------------------------------------------------------------------
Debug build of project `C:\Users\jagdeep\Downloads\pic16f72_sine_wave_ups_with_source_code_and_schematic_1585\New folder\ll.mcp' failed.
Language tool versions: MPASMWIN.exe v5.44, mplink.exe v4.42, mplib.exe v4.42
Preprocessor symbol `__DEBUG' is defined.
Wed Apr 03 21:38:47 2013
----------------------------------------------------------------------
BUILD FAILED
 

That is probably the most convoluted and confusing code I've ever seen. Is it a reverse assembly of somethng written in a high level language?

Your fundamental problem is it's too big to fit in the PICs memory. You can get rid of all those warnings by placing "errolevel -302" near the top of the code.
If you really want to stay with that style of programming, you can probably reduce the program size considerably by using packed values in your look-up tables. You can also remove the GIE bit code because the PIC does that in hardware when an interrupt occurs. You should also have at least one ORG statement.

Brian.
 
getting same error after adding "org 00h" :(
duke_pl said:
Add "ORG 00H" directive before "goto init"
Click to expand...

- - - Updated - - -

hii thanks for quick reply i downloaded this code but i want want to improve many things, but i can't because of tht error :( is there is any method to convert it to simple c code ??
betwixt said:
That is probably the most convoluted and confusing code I've ever seen. Is it a reverse assembly of somethng written in a high level language?

Your fundamental problem is it's too big to fit in the PICs memory. You can get rid of all those warnings by placing "errolevel -302" near the top of the code.
If you really want to stay with that style of programming, you can probably reduce the program size considerably by using packed values in your look-up tables. You can also remove the GIE bit code because the PIC does that in hardware when an interrupt occurs. You should also have at least one ORG statement.

Brian.
Click to expand...
 

Try this sequence:

ORG 00H
GOTO START ; jump to start of your program

ORG 04H ; interrupt vector
RETFIE ; return from interrupt

START ; start label

now rest of your program
GOTO INIT
...
...

Try another PIC with more flash memory, at least 4K.
 
The code looks to be writen in a high level language already and the listing shown is a disassembly of it. Even the worst source code would use meaningful labels and have proper comments in it. Personally, I would re-write it from scratch, trying to unravel all those un-named variables and what they do would be almost impossible and certainly take far longer than starting over again.

Unless you are prepared to devote lots of time to it, the only other solution would be to change to a PIC with more memory as duke_pl suggests but if you do that, make sure it uses the same pins for all the functions. Even trying to work out what pins are used for which purpose from that code would be difficult.

Brian.
 
hi, even i am getting similar problem. and i am a newbie to assembly code and PIC.
i am attaching my code here. and also the output where i get error of section .org_0 cannot fit the absolute section.
please help me.. m so badly stuck.

Thanks
Uttara
Code: 
[CODE]
; *****************************************************************************
#include <p18cxxx.inc>
#include "devices.inc"
#include "bootconfig.inc"
#include "preprocess.inc"
; *****************************************************************************

; *****************************************************************************
#define STX             0x0F            
#define ETX             0x04
#define DLE             0x05
#define NTX             0xFF
; *****************************************************************************

; *****************************************************************************
; RAM Address Map
CRCL                equ 0x00
CRCH                equ 0x01
RXDATA              equ 0x02
TXDATA              equ 0x03

; Framed Packet Format
; <STX>[<COMMAND><ADDRL><ADDRH><ADDRU><0x00><DATALEN><...DATA...>]<CRCL><CRCH><ETX>
COMMAND             equ 0x05        ; receive buffer
ADDRESS_L           equ 0x06
ADDRESS_H           equ 0x07
ADDRESS_U           equ 0x08
ADDRESS_X           equ 0x09
DATA_COUNTL         equ 0x0A
PACKET_DATA         equ 0x0B
DATA_COUNTH         equ 0x0B        ; only for certain commands
; *****************************************************************************

; *****************************************************************************
    errorlevel -311                 ; don't warn on HIGH() operator values >16-bits

#ifdef USE_SOFTBOOTWP
  #ifndef SOFTWP
    #define SOFTWP
  #endif
#endif

#ifdef USE_SOFTCONFIGWP
  #ifdef CONFIG_AS_FLASH
    #ifndef SOFTWP
      #define SOFTWP
    #endif
  #endif
#endif

#ifndef AppVector
    ; The application startup GOTO instruction will be written just before the Boot Block,
    ; courtesy of the host PC bootloader application.
    #define AppVector (BootloaderStart-.4)
#endif
; *****************************************************************************

 
; *****************************************************************************
#if BOOTLOADER_ADDRESS != 0
    ORG     0
    ; The following GOTO is not strictly necessary, but may startup faster
    ; for large microcontrollers running at extremely slow clock speeds.
    ;goto    BootloaderBreakCheck  

    ORG     BOOTLOADER_ADDRESS
BootloaderStart:
    bra     BootloadMode

; *****************************************************************************
; Determine if the application is supposed to be started or if we should
; go into bootloader mode.
;
; If RX pin is in BREAK state when we come out of MCLR reset, immediately 
; enter bootloader mode, even if there exists some application firmware in 
; program memory.
BootloaderBreakCheck:
    DigitalInput                ; set RX pin as digital input on certain parts
#ifdef INVERT_UART
    btfss   RXPORT, RXPIN
GotoAppVector:
    goto    AppVector           ; no BREAK state, attempt to start application
#else
    btfsc   RXPORT, RXPIN
GotoAppVector:
    goto    AppVector           ; no BREAK state, attempt to start application
#endif

BootloadMode:
    DigitalInput                ; set RX pin as digital input on certain parts
#else ; BOOTLOADER_ADDRESS == 0 ****************************************************************
    ORG     0
BootloaderStart:
    DigitalInput                ; set RX pin as digital input on certain parts
    movlw   low(AppVector)      ; load address of application reset vector
    bra     BootloaderBreakCheck

	ORG	    0x0008
HighPriorityInterruptVector:
	goto    AppHighIntVector    ; Re-map Interrupt vector

BootloaderBreakCheck:
#ifdef INVERT_UART
    btfsc   RXPORT, RXPIN
    bra     BootloadMode
#else
    btfss   RXPORT, RXPIN
    bra     BootloadMode
#endif
CheckAppVector:
    ; Read instruction at the application reset vector location. 
    ; If we read 0xFFFF, assume that the application firmware has
    ; not been programmed yet, so don't try going into application mode.
    movwf   TBLPTRL
    movlw   high(AppVector)
    movwf   TBLPTRH
    bra     CheckAppVector2

	ORG	    0x0018
LowPriorityInterruptVector:
	goto    AppLowIntVector     ; Re-map Interrupt vector

CheckAppVector2:
    movlw   upper(AppVector)
    movwf   TBLPTRU     
    tblrd   *+                  ; read instruction from program memory
    incfsz  TABLAT, W           ; if the lower byte != 0xFF, 
GotoAppVector:
    goto    AppVector           ; run application.

    tblrd   *+                  ; read instruction from program memory
    incfsz  TABLAT, W           ; if the lower byte == 0xFF but upper byte != 0xFF,
    bra     GotoAppVector       ; run application.
    ; otherwise, assume application firmware is not present because we read a NOP (0xFFFF).
    ; fall through to bootloader mode...
BootloadMode:
#endif ; end BOOTLOADER_ADDRESS == 0 ******************************************
    lfsr    FSR2, 0             ; for compatibility with Extended Instructions mode.

#ifdef USE_MAX_INTOSC
    movlw   b'01110000'         ; set INTOSC to maximum speed (usually 8MHz)
    iorwf   OSCCON, f
#endif

#ifdef USE_PLL
    #ifdef PLLEN
        #ifdef OSCTUNE
            bsf     OSCTUNE, PLLEN      ; enable PLL for faster internal clock
        #else
            ; 18F8680, 18F8585, 18F6680, and 18F6585 doesn't have OSCTUNE register.
            ; Instead, PLLEN bit is in OSCCON.
            bsf     OSCCON, PLLEN      ; enable PLL for faster internal clock
        #endif
    #else
        #ifdef SPLLEN
            bsf     OSCTUNE, SPLLEN     ; PIC18F14K50 has SPLLEN at bit 6
        #endif
    #endif
#endif

#ifdef INVERT_UART
    btfsc   RXPORT, RXPIN       ; wait for RX pin to go IDLE
    bra     $-2
#else
    btfss   RXPORT, RXPIN       ; wait for RX pin to go IDLE
    bra     $-2
#endif

#ifdef PPS_UTX_PIN
    banksel PPSCON
    ; unlock PPS registers
    movlw   0x55
    movwf   EECON2, ACCESS
    movlw   0xAA
    movwf   EECON2, ACCESS
    bcf     PPSCON, IOLOCK, BANKED

    ; assign UART RX/TX to PPS remappable pins
    movlw   PPS_UTX
    movwf   PPS_UTX_PIN, BANKED

    movlw   PPS_URX_PIN
    movwf   PPS_URX, BANKED

    ; lock PPS registers from inadvertent changes
    movlw   0x55
    movwf   EECON2, ACCESS
    movlw   0xAA
    movwf   EECON2, ACCESS
    bsf     PPSCON, IOLOCK, BANKED
    movlb   0x0F
#endif

    movlw   b'10010000'         ; Setup UART
    movwf   UxRCSTA
    movlw   b'00100110'         ; BRGH = 1, TXEN = 1
    movwf   UxTXSTA

#ifdef INVERT_UART
    bsf     UxBAUDCON, RXDTP
    bsf     UxBAUDCON, TXCKP
#endif

#ifdef BRG16
    bsf     UxBAUDCON, BRG16
    movlw   b'00000010'         ; 1:8 prescaler - no division required later (but no rounding possible)
#else
    movlw   b'00000011'         ; 1:16 prescaler - thus we only have to divide by 2 later on.
#endif
    movwf   T0CON

#ifdef PICDEM_LCD2
    bsf     LATB, LATB0         ; PICDEM LCD 2 demoboard requires RB0 high to enable MAX3221 TX output to PC.
    bcf     TRISB, TRISB0
#endif
; *****************************************************************************


; *****************************************************************************
#ifdef USE_AUTOBAUD
DoAutoBaud:
; ___    __________            ________
;    \__/          \__________/
;       |                     |
;       |-------- p ----------|
;
;   p = The number of instructions between the first and last
;           rising edge of the RS232 control sequence 0x0F. Other 
;       possible control sequences are 0x01, 0x03, 0x07, 0x1F, 
;       0x3F, 0x7F.
;
;   SPBRG = (p / 32) - 1    BRGH = 1, BRG16 = 0
;   SPBRG = (p / 8) - 1     BRGH = 1, BRG16 = 1

    bcf     UxRCSTA, CREN       ; Stop receiving
    movf    UxRCREG, W          ; Empty the buffer
    movf    UxRCREG, W

RetryAutoBaud:
    clrf    TMR0H               ; reset timer count value
    clrf    TMR0L
    bcf     INTCON, TMR0IF
    rcall   WaitForRise         ; wait for a start bit to pass by
    bsf     T0CON, TMR0ON       ; start timer counting for entire D7..D0 data bit period.
    rcall   WaitForRise         ; wait for stop bit
    bcf     T0CON, TMR0ON       ; stop the timer from counting further. 

    btfsc   INTCON, TMR0IF      ; if TMR0 overflowed, we did not get a good baud capture
    bra     RetryAutoBaud       ; try again

    #ifdef BRG16
    ; save new baud rate generator value
    movff   TMR0L, UxSPBRG      ; warning: must read TMR0L before TMR0H holds real data
    movff   TMR0H, UxSPBRGH
    #else 
    movff   TMR0L, UxSPBRG      ; warning: must read TMR0L before TMR0H holds real data
    ; TMR0H:TMR0L holds (p / 16).
    rrcf    TMR0H, w            ; divide by 2
    rrcf    UxSPBRG, F            
    btfss   STATUS, C           ; rounding
    decf    UxSPBRG, F    
    #endif

    bsf     UxRCSTA, CREN       ; start receiving

WaitForHostCommand:
    rcall   ReadHostByte        ; get start of transmission <STX>
    xorlw   STX
    bnz     DoAutoBaud          ; got something unexpected, perform autobaud
#else ; not using autobaud
    movlw   low(BAUDRG)         ; set fixed baud rate generator value
    movwf   UxSPBRG
    #ifdef UxSPBRGH
        #if high(BAUDRG) != 0
    movlw   high(BAUDRG)
    movwf   UxSPBRGH
        #endif
    #endif
    bsf     UxRCSTA, CREN       ; start receiving
DoAutoBaud:
WaitForHostCommand:
    rcall   ReadHostByte        ; get start of transmission <STX>
    xorlw   STX
    bnz     WaitForHostCommand  ; got something unexpected, keep waiting for <STX>
#endif ; end #ifdef USE_AUTOBAUD
        
; *****************************************************************************

; *****************************************************************************
; Read and parse packet data.
StartOfLine:
    movlw   STX                     ; send back start of response
    rcall   SendHostByte

    lfsr    FSR0, COMMAND-1         ; Point to the buffer
        
ReceiveDataLoop:
    rcall   ReadHostByte            ; Get the data
    xorlw   STX                     ; Check for an unexpected STX
    bz      StartOfLine             ; unexpected STX: abort packet and start over.

NoSTX:
    movf    RXDATA, W
    xorlw   ETX                     ; Check for a ETX
    bz      VerifyPacketCRC         ; Yes, verify CRC

NoETX:
    movf    RXDATA, W
    xorlw   DLE                     ; Check for a DLE
    bnz     AppendDataBuffer

    rcall   ReadHostByte            ; DLE received, get the next byte and store it
    
AppendDataBuffer:
    movff   RXDATA, PREINC0         ; store the data to the buffer
    bra     ReceiveDataLoop

VerifyPacketCRC:
    lfsr    FSR1, COMMAND
    clrf    CRCL
    clrf    CRCH
    movff   POSTDEC0, PRODH         ; Save host packet's CRCH to PRODH for later comparison
                                    ; CRCL is now available as INDF0
VerifyPacketCrcLoop:
    movf    POSTINC1, w
    rcall   AddCrc                  ; add new data to the CRC

    movf    FSR1H, w
    cpfseq  FSR0H
    bra     VerifyPacketCrcLoop     ; we aren't at the end of the received data yet, loop
    movf    FSR1L, w
    cpfseq  FSR0L
    bra     VerifyPacketCrcLoop     ; we aren't at the end of the received data yet, loop

    movf    CRCH, w
    cpfseq  PRODH
    bra     DoAutoBaud              ; invalid CRC, reset baud rate generator to re-sync with host
    movf    CRCL, w
    cpfseq  INDF0
    bra     DoAutoBaud              ; invalid CRC, reset baud rate generator to re-sync with host

; ***********************************************
; Pre-setup, common to all commands.
    clrf    CRCL
    clrf    CRCH

    movf    ADDRESS_L, W            ; Set all possible pointers
    movwf   TBLPTRL
#ifdef EEADR
    movwf   EEADR
#endif
    movf    ADDRESS_H, W
    movwf   TBLPTRH
#ifdef EEADRH
    movwf   EEADRH
#endif
    movff   ADDRESS_U, TBLPTRU
    lfsr    FSR0, PACKET_DATA
; ***********************************************

 

; ***********************************************
; Test the command field and sub-command.
CheckCommand:
    movlw   .10
    cpfslt  COMMAND
    bra     DoAutoBaud          ; invalid command - reset baud generator to re-sync with host

    ; This jump table must exist entirely within one 256 byte block of program memory.
;#if (($ & 0xFF) > (0xFF - .24))
    ; Too close to the end of a 256 byte boundary, push address forward to get code
    ; into the next 256 byte block.
 ;   messg   "Wasting some code space to ensure jump table is aligned."
  ;  ORG     $+(0x100 - ($ & 0xFF))
;#endif
JUMPTABLE_BEGIN:
    movf    PCL, w              ; 0 do a read of PCL to set PCLATU:PCLATH to current program counter.
    rlncf   COMMAND, W          ; 2 multiply COMMAND by 2 (each BRA instruction takes 2 bytes on PIC18)
    addwf   PCL, F              ; 4 Jump in command jump table based on COMMAND from host
    bra     BootloaderInfo      ; 6 00h
    bra     ReadFlash           ; 8 01h
    bra     VerifyFlash         ; 10 02h
    bra     EraseFlash          ; 12 03h
    bra     WriteFlash          ; 14 04h
    bra     ReadEeprom          ; 16 05h
    bra     WriteEeprom         ; 18 06h
    bra     WriteConfig         ; 20 07h
    bra     GotoAppVector       ; 22 08h
    reset                       ; 24 09h

;#if (JUMPTABLE_BEGIN & 0xFF) > ($ & 0xFF)
 ;   error "Jump table is not aligned to fit within a single 256 byte address range."
;#endif
; *****************************************************************************

#ifdef INVERT_UART
WaitForRise:
    clrwdt

WaitForRiseLoop:
    btfsc   INTCON, TMR0IF  ; if TMR0 overflowed, we did not get a good baud capture
    return                  ; abort

    btfss   RXPORT, RXPIN   ; Wait for a falling edge
    bra     WaitForRiseLoop

WtSR:
    btfsc   RXPORT, RXPIN   ; Wait for starting edge
    bra     WtSR
    return
#else ; not inverted UART pins
WaitForRise:
    clrwdt

WaitForRiseLoop
    btfsc   INTCON, TMR0IF  ; if TMR0 overflowed, we did not get a good baud capture
    return                  ; abort

    btfsc   RXPORT, RXPIN   ; Wait for a falling edge
    bra     WaitForRiseLoop

WtSR:
    btfss   RXPORT, RXPIN   ; Wait for rising edge
    bra     WtSR
    return
#endif ; end #ifdef INVERT_UART
; *****************************************************************************

; 16-bit CCITT CRC
; Adds WREG byte to the CRC checksum CRCH:CRCL. WREG destroyed on return.
AddCrc:                           ; Init: CRCH = HHHH hhhh, CRCL = LLLL llll
    xorwf   CRCH, w               ; Pre:  HHHH hhhh     WREG =      IIII iiii
    movff   CRCL, CRCH            ; Pre:  LLLL llll     CRCH =      LLLL llll
    movwf   CRCL                  ; Pre:  IIII iiii     CRCL =      IIII iiii
    swapf   WREG                  ; Pre:  IIII iiii     WREG =      iiii IIII
    andlw   0x0F                  ; Pre:  iiii IIII     WREG =      0000 IIII
    xorwf   CRCL, f               ; Pre:  IIII iiii     CRCL =      IIII jjjj
    swapf   CRCL, w               ; Pre:  IIII jjjj     WREG =      jjjj IIII
    andlw   0xF0                  ; Pre:  jjjj IIII     WREG =      jjjj 0000
    xorwf   CRCH, f               ; Pre:  LLLL llll     CRCH =      MMMM llll
    swapf   CRCL, w               ; Pre:  IIII jjjj     WREG =      jjjj IIII
    rlncf   WREG, w               ; Pre:  jjjj IIII     WREG =      jjjI IIIj
    xorwf   CRCH, f               ; Pre:  MMMM llll     CRCH =      XXXN mmmm
    andlw   b'11100000'           ; Pre:  jjjI IIIj     WREG =      jjj0 0000
    xorwf   CRCH, f               ; Pre:  jjj0 0000     CRCH =      MMMN mmmm
    xorwf   CRCL, f               ; Pre:  MMMN mmmm     CRCL =      JJJI jjjj
    return

; ***********************************************
; Commands
; ***********************************************

; Provides information about the Bootloader to the host PC software.
BootInfoBlock:
    db      low(BOOTBLOCKSIZE), high(BOOTBLOCKSIZE)
    db      MAJOR_VERSION, MINOR_VERSION
    db      0xFF, 0x84             ; command mask : family id 
    db      low(BootloaderStart), high(BootloaderStart)
    db      upper(BootloaderStart), 0 
BootInfoBlockEnd:

; In:   <STX>[<0x00>]<CRCL><CRCH><ETX>
; Out:  <STX><BOOTBYTESL><BOOTBYTESH><VERL><VERH><STARTBOOTL><STARTBOOTH><STARTBOOTU><0x00><CRCL><CRCH><ETX>
BootloaderInfo:
    movlw   low(BootInfoBlock)
    movwf   TBLPTRL
    movlw   high(BootInfoBlock)
    movwf   TBLPTRH
    movlw   upper(BootInfoBlock)
    movwf   TBLPTRU

    movlw   (BootInfoBlockEnd - BootInfoBlock)
    movwf   DATA_COUNTL
    clrf    DATA_COUNTH
    ;; fall through to ReadFlash code -- send Bootloader Information Block from FLASH.

; In:   <STX>[<0x01><ADDRL><ADDRH><ADDRU><0x00><BYTESL><BYTESH>]<CRCL><CRCH><ETX>
; Out:  <STX>[<DATA>...]<CRCL><CRCH><ETX>
ReadFlash:
    tblrd   *+                  ; read from FLASH memory into TABLAT
    movf    TABLAT, w
    rcall   SendEscapeByte
    rcall   AddCrc

    decf    DATA_COUNTL, f      ; decrement counter
    movlw   0
    subwfb  DATA_COUNTH, f

    movf    DATA_COUNTL, w      ; DATA_COUNTH:DATA_COUNTH == 0?
    iorwf   DATA_COUNTH, w
    bnz     ReadFlash           ; no, loop
    bra     SendChecksum        ; yes, send end of packet

; In:   <STX>[<0x02><ADDRL><ADDRH><ADDRU><0x00><BLOCKSL><BLOCKSH>]<CRCL><CRCH><ETX>
; Out:  <STX>[<CRCL1><CRCH1>...<CRCLn><CRCHn>]<ETX>
VerifyFlash:
    tblrd   *+
    movf    TABLAT, w    
    rcall   AddCrc

    movf    TBLPTRL, w          ; have we crossed into the next block?
#if ERASE_FLASH_BLOCKSIZE > .255
    bnz     VerifyFlash
    movf    TBLPTRH, w
    andlw   high(ERASE_FLASH_BLOCKSIZE-1)
#else
    andlw   (ERASE_FLASH_BLOCKSIZE-1)    
#endif
    bnz     VerifyFlash

    movf    CRCL, w
    call    SendEscapeByte
    movf    CRCH, w
    call    SendEscapeByte

    decf    DATA_COUNTL, f      ; decrement counter
    movlw   0
    subwfb  DATA_COUNTH, f

    movf    DATA_COUNTL, w      ; DATA_COUNTH:DATA_COUNTH == 0?
    iorwf   DATA_COUNTH, w
    bnz     VerifyFlash         ; no, loop
    bra     SendETX             ; yes, send end of packet

#ifdef SOFTWP
    reset                       ; this code -should- never be executed, but 
    reset                       ; just in case of errant execution or buggy
    reset                       ; firmware, these reset instructions may protect
    reset                       ; against accidental erases.
#endif

; In:   <STX>[<0x03><ADDRL><ADDRH><ADDRU><0x00><PAGESL>]<CRCL><CRCH><ETX>
; Out:  <STX>[<0x03>]<CRCL><CRCH><ETX>
EraseFlash:
#ifdef SOFTWP
  #define ERASE_ADDRESS_MASK  (~(ERASE_FLASH_BLOCKSIZE-1))
  #if upper(ERASE_ADDRESS_MASK) != 0xFF
    movlw   upper(ERASE_ADDRESS_MASK)    ; force starting address to land on a FLASH Erase Block boundary
    andwf   TBLPTRU, f
  #endif
  #if high(ERASE_ADDRESS_MASK) != 0xFF
    movlw   high(ERASE_ADDRESS_MASK)    ; force starting address to land on a FLASH Erase Block boundary
    andwf   TBLPTRH, f
  #endif
  #if low(ERASE_ADDRESS_MASK) != 0xFF
    movlw   low(ERASE_ADDRESS_MASK)     ; force starting address to land on a FLASH Erase Block boundary
    andwf   TBLPTRL, f
  #endif

    ; Verify Erase Address does not attempt to erase beyond the end of FLASH memory
    movlw   low(END_FLASH)
    subwf   TBLPTRL, w
    movlw   high(END_FLASH)
    subwfb  TBLPTRH, w
    movlw   upper(END_FLASH)
    subwfb  TBLPTRU, w
    bn      EraseEndFlashAddressOkay

    clrf    EECON1              ; inhibit writes for this block
    bra     NextEraseBlock      ; move on to next erase block
#endif ; end #ifdef USE_SOFTBOOTWP

EraseEndFlashAddressOkay:
#ifdef USE_SOFTCONFIGWP
    #ifdef CONFIG_AS_FLASH
    movlw   low(END_FLASH - ERASE_FLASH_BLOCKSIZE)
    subwf   TBLPTRL, w
    movlw   high(END_FLASH - ERASE_FLASH_BLOCKSIZE)
    subwfb  TBLPTRH, w
    movlw   upper(END_FLASH - ERASE_FLASH_BLOCKSIZE)
    subwfb  TBLPTRU, w
    bn      EraseConfigAddressOkay

    clrf    EECON1              ; inhibit writes for this block
    bra     NextEraseBlock      ; move on to next erase block

EraseConfigAddressOkay:
    #endif ; end CONFIG_AS_FLASH
#endif ; end USE_SOFTCONFIGWP

#ifdef USE_SOFTBOOTWP
    movlw   low(BOOTLOADER_ADDRESS)
    subwf   TBLPTRL, w
    movlw   high(BOOTLOADER_ADDRESS)
    subwfb  TBLPTRH, w
    movlw   upper(BOOTLOADER_ADDRESS)
    subwfb  TBLPTRU, w
    bn      EraseAddressOkay

    movlw   low(BOOTLOADER_ADDRESS + BOOTBLOCKSIZE)
    subwf   TBLPTRL, w
    movlw   high(BOOTLOADER_ADDRESS + BOOTBLOCKSIZE)
    subwfb  TBLPTRH, w
    movlw   upper(BOOTLOADER_ADDRESS + BOOTBLOCKSIZE)
    subwfb  TBLPTRU, w
    bnn     EraseAddressOkay

    clrf    EECON1              ; inhibit writes for this block
    bra     NextEraseBlock      ; move on to next erase block

    reset                       ; this code -should- never be executed, but 
    reset                       ; just in case of errant execution or buggy
    reset                       ; firmware, these reset instruction may protect
    reset                       ; against accidental writes.
#endif

EraseAddressOkay:
#ifdef EEADR
    movlw   b'10010100'         ; setup FLASH erase
#else
    movlw   b'00010100'         ; setup FLASH erase for J device (no EEPROM bit)
#endif
    movwf   EECON1

    rcall   StartWrite          ; erase the page

NextEraseBlock:
    ; Decrement address by erase block size
#if ERASE_FLASH_BLOCKSIZE >= .256
    movlw   high(ERASE_FLASH_BLOCKSIZE)
    subwf   TBLPTRH, F
    clrf    WREG
    subwfb  TBLPTRU, F
#else
    movlw   ERASE_FLASH_BLOCKSIZE
    subwf   TBLPTRL, F
    clrf    WREG
    subwfb  TBLPTRH, F
    subwfb  TBLPTRU, F
#endif

    decfsz  DATA_COUNTL, F
    bra     EraseFlash    
    bra     SendAcknowledge     ; All done, send acknowledgement packet

#ifdef SOFTWP
    reset                       ; this code -should- never be executed, but 
    reset                       ; just in case of errant execution or buggy
    reset                       ; firmware, these reset instructions may protect
    reset                       ; against accidental writes.
#endif

; In:   <STX>[<0x04><ADDRL><ADDRH><ADDRU><0x00><BLOCKSL><DATA>...]<CRCL><CRCH><ETX>
; Out:  <STX>[<0x04>]<CRCL><CRCH><ETX>
WriteFlash:
#ifdef SOFTWP
  #define WRITE_ADDRESS_MASK (~(WRITE_FLASH_BLOCKSIZE-1))
  #if upper(WRITE_ADDRESS_MASK) != 0xFF
    movlw   upper(WRITE_ADDRESS_MASK)    ; force starting address to land on a FLASH Write Block boundary
    andwf   TBLPTRU, f
  #endif
  #if high(WRITE_ADDRESS_MASK) != 0xFF
    movlw   high(WRITE_ADDRESS_MASK)    ; force starting address to land on a FLASH Write Block boundary
    andwf   TBLPTRH, f
  #endif
  #if low(WRITE_ADDRESS_MASK) != 0xFF
    movlw   low(WRITE_ADDRESS_MASK)     ; force starting address to land on a FLASH Write Block boundary
    andwf   TBLPTRL, f
  #endif

    ; Verify Write Address does not attempt to write beyond the end of FLASH memory
    movlw   low(END_FLASH)
    subwf   TBLPTRL, w
    movlw   high(END_FLASH)
    subwfb  TBLPTRH, w
    movlw   upper(END_FLASH)
    subwfb  TBLPTRU, w
    bn      WriteEndFlashAddressOkay

    clrf    EECON1              ; inhibit writes for this block
    bra     LoadHoldingRegisters; fake the write so we can move on to real writes
#endif ; end #ifdef SOFTWP

WriteEndFlashAddressOkay:
#ifdef USE_SOFTCONFIGWP
    #ifdef CONFIG_AS_FLASH
    movlw   low(END_FLASH - ERASE_FLASH_BLOCKSIZE)
    subwf   TBLPTRL, w
    movlw   high(END_FLASH - ERASE_FLASH_BLOCKSIZE)
    subwfb  TBLPTRH, w
    movlw   upper(END_FLASH - ERASE_FLASH_BLOCKSIZE)
    subwfb  TBLPTRU, w
    bn      WriteConfigAddressOkay

    clrf    EECON1              ; inhibit writes for this block
    bra     LoadHoldingRegisters; fake the write so we can move on to real writes

WriteConfigAddressOkay:
    #endif ; end CONFIG_AS_FLASH
#endif ; end USE_SOFTCONFIGWP

#ifdef USE_SOFTBOOTWP
    movlw   low(BOOTLOADER_ADDRESS)
    subwf   TBLPTRL, w
    movlw   high(BOOTLOADER_ADDRESS)
    subwfb  TBLPTRH, w
    movlw   upper(BOOTLOADER_ADDRESS)
    subwfb  TBLPTRU, w
    bn      WriteAddressOkay

    movlw   low(BOOTLOADER_ADDRESS + BOOTBLOCKSIZE)
    subwf   TBLPTRL, w
    movlw   high(BOOTLOADER_ADDRESS + BOOTBLOCKSIZE)
    subwfb  TBLPTRH, w
    movlw   upper(BOOTLOADER_ADDRESS + BOOTBLOCKSIZE)
    subwfb  TBLPTRU, w
    bnn     WriteAddressOkay

    clrf    EECON1                      ; inhibit writes for this block
    bra     LoadHoldingRegisters        ; fake the write so we can move on to real writes

    reset                       ; this code -should- never be executed, but 
    reset                       ; just in case of errant execution or buggy
    reset                       ; firmware, these reset instruction may protect
    reset                       ; against accidental writes.
#endif

WriteAddressOkay:
#ifdef EEADR
    movlw   b'10000100'         ; Setup FLASH writes
#else
    movlw   b'00000100'         ; Setup FLASH writes for J device (no EEPROM bit)
#endif
    movwf   EECON1

LoadHoldingRegisters:
    movff   POSTINC0, TABLAT    ; Load the holding registers
    pmwtpi                      ; Same as tblwt *+

    movf    TBLPTRL, w          ; have we crossed into the next write block?
    andlw   (WRITE_FLASH_BLOCKSIZE-1)
    bnz     LoadHoldingRegisters; Not finished writing holding registers, repeat

    tblrd   *-                  ; Point back into the block to write data
    rcall   StartWrite          ; initiate a page write
    tblrd   *+                  ; Restore pointer for loading holding registers with next block

    decfsz  DATA_COUNTL, F      
    bra     WriteFlash          ; Not finished writing all blocks, repeat
    bra     SendAcknowledge     ; all done, send ACK packet

; In:   <STX>[<0x05><ADDRL><ADDRH><0x00><0x00><BYTESL><BYTESH>]<CRCL><CRCH><ETX>
; Out:  <STX>[<DATA>...]<CRCL><CRCH><ETX>
#ifdef EEADR                ; some devices do not have EEPROM, so no need for this code
ReadEeprom:
    clrf    EECON1 
ReadEepromLoop:
    bsf     EECON1, RD          ; Read the data
    movf    EEDATA, w
    #ifdef EEADRH
    infsnz  EEADR, F            ; Adjust EEDATA pointer
    incf    EEADRH, F
    #else
    incf    EEADR, F            ; Adjust EEDATA pointer
    #endif
    rcall   SendEscapeByte
    rcall   AddCrc

    #ifdef EEADRH
    decf    DATA_COUNTL, f      ; decrement counter
    movlw   0
    subwfb  DATA_COUNTH, f

    movf    DATA_COUNTL, w      ; DATA_COUNTH:DATA_COUNTH == 0?
    iorwf   DATA_COUNTH, w
    bnz     ReadEepromLoop      ; no, loop
    bra     SendChecksum        ; yes, send end of packet
    #else
    decfsz  DATA_COUNTL, F
    bra     ReadEepromLoop      ; Not finished then repeat
    bra     SendChecksum
    #endif
#endif ; end #ifdef EEADR

; In:   <STX>[<0x06><ADDRL><ADDRH><0x00><0x00><BYTESL><BYTESH><DATA>...]<CRCL><CRCH><ETX>
; Out:  <STX>[<0x06>]<CRCL><CRCH><ETX>
#ifdef EEADR                ; some devices do not have EEPROM, so no need for this code
WriteEeprom:
    movlw   b'00000100'     ; Setup for EEPROM data writes
    movwf   EECON1

WriteEepromLoop:
    movff   PREINC0, EEDATA
    rcall   StartWrite      

    btfsc   EECON1, WR      ; wait for write to complete before moving to next address
    bra     $-2

    #ifdef EEADRH
    infsnz  EEADR, F        ; Adjust EEDATA pointer
    incf    EEADRH, F
    #else
    incf    EEADR, f        ; Adjust EEDATA pointer
    #endif

    #ifdef EEADRH
    decf    DATA_COUNTL, f      ; decrement counter
    movlw   0
    subwfb  DATA_COUNTH, f

    movf    DATA_COUNTL, w      ; DATA_COUNTH:DATA_COUNTH == 0?
    iorwf   DATA_COUNTH, w
    bnz     WriteEepromLoop     ; no, loop
    bra     SendAcknowledge     ; yes, send end of packet
    #else
    decfsz  DATA_COUNTL, f
    bra     WriteEepromLoop
    bra     SendAcknowledge
    #endif
#endif ; end #ifdef EEADR
 
; In:   <STX>[<0x07><ADDRL><ADDRH><ADDRU><0x00><BYTES><DATA>...]<CRCL><CRCH><ETX>
; Out:  <STX>[<0x07>]<CRCL><CRCH><ETX>
#ifndef CONFIG_AS_FLASH     ; J flash devices store config words in FLASH, so no need for this code
    #ifndef USE_SOFTCONFIGWP
WriteConfig:
    movlw   b'11000100'
    movwf   EECON1
    tblrd   *               ; read existing value from config memory

WriteConfigLoop:
    movf    POSTINC0, w
    cpfseq  TABLAT          ; is the proposed value already the same as existing value?
    rcall   TableWriteWREG  ; write config memory only if necessary (save time and endurance)
    tblrd   +*              ; increment table pointer to next address and read existing value
    decfsz  DATA_COUNTL, F
    bra     WriteConfigLoop ; If more data available in packet, keep looping

    bra     SendAcknowledge ; Send acknowledge
    #endif ; end #ifndef USE_SOFTCONFIGWP
#endif ; end #ifndef CONFIG_AS_FLASH
    
;************************************************

; ***********************************************
; Send an acknowledgement packet back
;
; <STX><COMMAND><CRCL><CRCH><ETX>

; Some devices only have config words as FLASH memory. Some devices don't have EEPROM.
; For these devices, we can save code by jumping directly to sending back an
; acknowledgement packet if the PC application erroneously requests them.
#ifdef CONFIG_AS_FLASH
WriteConfig:
#else
  #ifdef USE_SOFTCONFIGWP
WriteConfig:
  #endif
#endif ; end #ifdef CONFIG_AS_FLASH

#ifndef EEADR
ReadEeprom:
WriteEeprom:
#endif

SendAcknowledge:
    clrf    EECON1              ; inhibit write cycles to FLASH memory

    movf    COMMAND, w
    rcall   SendEscapeByte      ; Send only the command byte (acknowledge packet)
    rcall   AddCrc

SendChecksum:
    movf    CRCL, W
    rcall   SendEscapeByte

    movf    CRCH, W
    rcall   SendEscapeByte

SendETX:
    movlw   ETX             ; Send stop condition
    rcall   SendHostByte

    bra     WaitForHostCommand
; *****************************************************************************




; *****************************************************************************
; Write a byte to the serial port while escaping control characters with a DLE
; first.
SendEscapeByte:
    movwf   TXDATA          ; Save the data
 
    xorlw   STX             ; Check for a STX
    bz      WrDLE           ; No, continue WrNext

    movf    TXDATA, W       
    xorlw   ETX             ; Check for a ETX
    bz      WrDLE           ; No, continue WrNext

    movf    TXDATA, W       
    xorlw   DLE             ; Check for a DLE
    bnz     WrNext          ; No, continue WrNext

WrDLE:
    movlw   DLE             ; Yes, send DLE first
    rcall   SendHostByte

WrNext:
    movf    TXDATA, W       ; Then send STX

SendHostByte:
    clrwdt
    btfss   UxPIR, UxTXIF      ; Write only if TXREG is ready
    bra     $-2
    
    movwf   UxTXREG           ; Start sending

    return
; *****************************************************************************




; *****************************************************************************
ReadHostByte:
    btfsc   UxRCSTA, OERR       ; Reset on overun
    reset

WaitForHostByte:
    clrwdt
    btfss   UxPIR, UxRCIF       ; Wait for data from RS232
    bra     WaitForHostByte

    movf    UxRCREG, W          ; Save the data
    movwf   RXDATA
 
    return
; *****************************************************************************

    reset                       ; this code -should- never be executed, but 
    reset                       ; just in case of errant execution or buggy
    reset                       ; firmware, these instructions may protect
    clrf    EECON1              ; against accidental erase/write operations.

; *****************************************************************************
; Unlock and start the write or erase sequence.
TableWriteWREG:
    movwf   TABLAT
    tblwt   *

StartWrite:
    clrwdt

    movlw   0x55            ; Unlock
    movwf   EECON2
    movlw   0xAA
    movwf   EECON2
    bsf     EECON1, WR      ; Start the write
    nop

    return
; *****************************************************************************

    END
[/CODE]


Code: 
----------------------------------------------------------------------
Debug build of project `D:\product data\AN1310 bootloader microchip\PIC18 Bootloader\PIC18 Bootloader.mcp' started.
Language tool versions: MPASMWIN.exe v5.51, mplink.exe v4.49, mplib.exe v4.49
Preprocessor symbol `__DEBUG' is defined.
Sat Jan 04 12:49:45 2014
----------------------------------------------------------------------
Clean: Deleting intermediary and output files.
Clean: Deleted file "D:\product data\AN1310 bootloader microchip\PIC18 Bootloader\PIC18 Bootloader.o".
Clean: Deleted file "D:\product data\AN1310 bootloader microchip\PIC18 Bootloader\PIC18 Bootloader.err".
Clean: Deleted file "D:\product data\AN1310 bootloader microchip\PIC18 Bootloader\PIC18 Bootloader.hex".
Clean: Deleted file "D:\product data\AN1310 bootloader microchip\PIC18 Bootloader\PIC18 Bootloader.lst".
Clean: Deleted file "D:\product data\AN1310 bootloader microchip\PIC18 Bootloader\PIC18 Bootloader.cof".
Clean: Deleted file "D:\product data\AN1310 bootloader microchip\PIC18 Bootloader\PIC18 Bootloader.map".
Clean: Done.
Executing: "C:\Program Files\Microchip\MPASM Suite\MPASMWIN.exe" /q /p18F2620 "PIC18 Bootloader.asm" /l"PIC18 Bootloader.lst" /e"PIC18 Bootloader.err" /d__DEBUG=1 /y
Executing: "C:\Program Files\Microchip\MPASM Suite\mplink.exe" /p18F2620 -g "PIC18 Bootloader.o" /u_EXTENDEDMODE /u_DEBUG /z__MPLAB_BUILD=1 /z__MPLAB_DEBUG=1 /m"PIC18 Bootloader.map" /w /o"PIC18 Bootloader.cof" /x
MPLINK 4.49, Linker
Device Database Version 1.14
Copyright (c) 1998-2011 Microchip Technology Inc.
Error - section '.org_0' can not fit the absolute section. Section '.org_0' start=0x00000000, length=0x00000000
Errors    : 1

Link step failed.
----------------------------------------------------------------------
Debug build of project `D:\product data\AN1310 bootloader microchip\PIC18 Bootloader\PIC18 Bootloader.mcp' failed.
Language tool versions: MPASMWIN.exe v5.51, mplink.exe v4.49, mplib.exe v4.49
Preprocessor symbol `__DEBUG' is defined.
Sat Jan 04 12:49:46 2014
----------------------------------------------------------------------
BUILD FAILED
 

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