Error reported in .vh files (include files) during synthesis with Precision

[dpaul]

Hi,

I see a significant amount of errors in the verilog header files that are used as includes in my design.

They are perfectly legal system verilog constructs.
e.g- localparam logic [31:0] NC_DEBUG_CTRL_CIA_BLDID = 32'h1303_2800; <-- Error line

Then I see errors as 'Illegal Scope of Declaration'.
e.g- localparam BRKPT_CTRL_ABP_NUM = 4; <-- Error line

In the Precision TCL script I am parsing the header files as:
add_input_file -format SystemVerilog includes/external_constants_include.vh

I also used the search path command as:
setup_design -search_path { "/home/src/includes"}

I had no problems with these include files during simulation with VCS.

Can anybody give me a clue why this is happening and what should I do to get rid of them?

More info/the entire TCL script can be made available on request.

Thanks,
dpaul

 

[dpaul]

Let me put the question in a different way if it helps.

All the `include files are contained in a dir as ~includes/
These files have the extension .vh
There are some SystemVerilog constructs in those .vh files (as I have given 1 example above).

I am including the search paths and library files using the following commands:

setup_design -search_path { "/home/dpaul/nanocore/rev28462_fpga/src/includes" \
                            "/home/dpaul/nanocore/rev28462_fpga/src/fpga" }
setup_design -y /home/shared/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims
setup_design -y /home/shared/Xilinx/14.4/ISE_DS/ISE/verilog/src/XilinxCoreLib
setup_design -libext +.v+.sv

No errors are shown for the SystemVerilog constructs in the RTL design files.
Am I missing some library files?
Am I missing some paths to be included?