Feb 21, 2014 #1 B BartlebyScrivener Member level 5 Joined Feb 8, 2012 Messages 90 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 2,081 Using systemverilog, I am trying to work out if one number is an integer multiple of another. An example is below. Code: l_datain[i][4] = ((i % X_NODES) == 0) ? 'z : l_dataout[i-1][2]; If Code: i is some multiple of Code: X_NODES connect Code: 'z else connect something else. Once upon a time this code allowed me to simulate, but now I get the following error Code: Error: Modulus operator invalid for REAL. X_NODES is passed as a parameter Code: parameter X_NODES = `X_NODES, from somewhere where it is defined Code: `define X_NODES 8 Where is it failing? Thank you!
Using systemverilog, I am trying to work out if one number is an integer multiple of another. An example is below. Code: l_datain[i][4] = ((i % X_NODES) == 0) ? 'z : l_dataout[i-1][2]; If Code: i is some multiple of Code: X_NODES connect Code: 'z else connect something else. Once upon a time this code allowed me to simulate, but now I get the following error Code: Error: Modulus operator invalid for REAL. X_NODES is passed as a parameter Code: parameter X_NODES = `X_NODES, from somewhere where it is defined Code: `define X_NODES 8 Where is it failing? Thank you!
Feb 21, 2014 #2 mrflibble Advanced Member level 5 Joined Apr 19, 2010 Messages 2,720 Helped 679 Reputation 1,360 Reaction score 652 Trophy points 1,393 Activity points 19,551 Try either one of these: Code: parameter integer X_NODES = `X_NODES, localparam integer X_NODES = `X_NODES,
Try either one of these: Code: parameter integer X_NODES = `X_NODES, localparam integer X_NODES = `X_NODES,