[SOLVED] Error: Modulus operator invalid for REAL.

[BartlebyScrivener]

Using systemverilog, I am trying to work out if one number is an integer multiple of another. An example is below.

l_datain[i][4] = ((i % X_NODES) == 0) ? 'z : l_dataout[i-1][2];

If

i

is some multiple of

X_NODES

connect

'z

else connect something else.

Once upon a time this code allowed me to simulate, but now I get the following error

Error: Modulus operator invalid for REAL.

X_NODES is passed as a parameter

parameter X_NODES = `X_NODES,

from somewhere where it is defined

`define X_NODES 8

Where is it failing?

Thank you!

 

[mrflibble]

Try either one of these:

parameter integer X_NODES = `X_NODES,

localparam integer X_NODES = `X_NODES,