soujanya04
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Hi all,
I am using xilinx ISE 14.7 and spartan 3e
The part of my VHDL code where I got error is::
where
and packages used are::
Error I got in isim simulation is:
Error when synthesised :
Please help me with this issue., what is the error and problem in my code?
I am using xilinx ISE 14.7 and spartan 3e
The part of my VHDL code where I got error is::
Code VHDL - [expand] 1 2 3 4 5 if (kk<=x"010000")then bh := x"00"; else bh := x"01"; end if;
where
Code VHDL - [expand] 1 2 variable kk: sfixed(22 downto -1); variable bh: sfixed(6 downto -1);
and packages used are::
Code VHDL - [expand] 1 2 3 library ieee_proposed; use ieee_proposed.fixed_float_types.all; use ieee_proposed.fixed_pkg.all;
Error I got in isim simulation is:
Warning: fixed_pkg:"<=": metavalue detected, returning FALSE
Error when synthesised :
ERROR:Xst:1749 - "D:/Xilinx proj files/mtech_2/fixed_pkg_c.vhdl" line 2083: error: fixed_pkg: Vector passed using a "to" range, expected is "downto"
Please help me with this issue., what is the error and problem in my code?
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