abhineet22 said:
process(clock,reset)
begin
if clock'event and clock='1'and reset='0'then
if rd_wr='0'then
data<=temp_data_out;
else
temp_data_in<=data;
end if;
else
data<=temp_data_out;
end if;
end process;
end rtl;
I think that the problem is with 2 parts. I will try to explain the first part.
The problem is that you are "confusing" the compiler when you lump lots of conditions in the process statement.
i.e. --> if clock'event and clock='1'and reset='0'then
I assume that you want a circuit with synchronous reset.
Typically we isolate the edge triggering and the reset signal.
i.e.
if (clock'event and clock = '1') then
if (reset = '1') then
data<=temp_data_out;
elsif (rd_wr = '0') then
data<=temp_data_out;
else
temp_data_in<=data;
end if;
end if;
Added after 6 minutes:
abhineet22 said:
architecture behav of byte_register is
begin
process(Clock,Reset, Datain)
begin
if(Reset='1') then
Dataout<="00000000";
elsif(Reset='0' and Enable = '1' and clock = '1' and clock'event) then
Dataout<=Datain;
end if;
end process;
end behav;
The second part is of the same argument with the first.
i.e. --> elsif(Reset='0' and Enable = '1' and clock = '1' and clock'event) then
This time, it seemed that you want an asynchonrous reset.
Prehaps, you can change that to:
process(Clock,Reset, Datain, Enable)
begin
if(Reset='1') then
Dataout<="00000000";
elsif(clock = '1' and clock'event) then
if (Enable = '1') then
Dataout<=Datain;
end if;
end if;
end process;
PS: you have forgotten to add the Enable signal in the process list