Error in verilog code for stopwatch

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I am getting error in verilog code while compiling using Quartus II as under
Error (10119): Verilog HDL Loop Statement error at DE1_SOC_golden_top.v(313): loop with non-constant loop condition must terminate within 250 iterations
Click to expand...

Line 313 is

Code: 
#50 clock = ~clock;

code for the test bench module is

Code Verilog - [expand]
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// Outputs
 wire [3:0] d0;
 wire [3:0] d1;
 wire [3:0] d2;
 
 // Instantiate the Unit Under Test (UUT)
 stopwatch uut (
  .clock(clock), 
  .reset(reset), 
  .start(start), 
  .d0(d0), 
  .d1(d1), 
  .d2(d2)
 );
 
initial
  begin
   clock = 0;
    forever
     #50 clock = ~clock;
  end
 
 initial begin
  // Initialize Inputs
  reset = 0;
  start = 0;
 
  // Wait 100 ns for global reset to finish
  #100;
  reset = 1;
  #100;
  reset = 0;
  #100;
  start = 1;
  // Add stimulus here
 end

Any suggestions for rectifying the same. I am generating a 0.1 second delay..
 
Last edited by a moderator:

Looks like you tried to compile the testbench in a synthesisor. You cannot synthesise this code, its only for simulation.
 
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    Nyom

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You can't synthesize a #<delay_value> statement. It is meaningless to the synthesis tool as time can't be synthesized into hardware.
 
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    Nyom

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you are right.. actual code is as under but i am trying to comile and run it using Quatus for Altera DE1 board.. I am new to it. What I thought I have a sample project which has functional and has a pin plannar and qpf file.. What I was trying to do was to embed the test code which i shared above and call this module. If this is wrong, then how do I compile the code

Code: 
module stopwatch(
    input clock,
    input reset,
    input start,
    output a, b, c, d, e, f, g, dp,
    output [3:0] an
);
 
reg [3:0] reg_d0, reg_d1, reg_d2, reg_d3; //registers that will hold the individual counts
reg [22:0] ticker; //23 bits needed to count up to 5M bits
wire click;
 
 
//the mod 5M clock to generate a tick ever 0.1 second
 
always @ (posedge clock or posedge reset)
begin
 if(reset)
 
  ticker <= 0;
 
 else if(ticker == 5000000) //if it reaches the desired max value reset it
  ticker <= 0;
 else if(start) //only start if the input is set high
  ticker <= ticker + 1;
end
 
assign click = ((ticker == 5000000)?1'b1:1'b0); //click to be assigned high every 0.1 second
 
always @ (posedge clock or posedge reset)
begin
 if (reset)
  begin
   reg_d0 <= 0;
   reg_d1 <= 0;
   reg_d2 <= 0;
   reg_d3 <= 0;
  end
   
 else if (click) //increment at every click
  begin
   if(reg_d0 == 9) //xxx9 - the 0.1 second digit
   begin  //if_1
    reg_d0 <= 0;
     
    if (reg_d1 == 9) //xx99 
    begin  // if_2
     reg_d1 <= 0;
     if (reg_d2 == 5) //x599 - the two digit seconds digits
     begin //if_3
      reg_d2 <= 0;
      if(reg_d3 == 9) //9599 - The minute digit
       reg_d3 <= 0;
      else
       reg_d3 <= reg_d3 + 1;
     end
     else //else_3
      reg_d2 <= reg_d2 + 1;
    end
     
    else //else_2
     reg_d1 <= reg_d1 + 1;
   end
    
   else //else_1
    reg_d0 <= reg_d0 + 1;
  end
end
 
//The Circuit for Multiplexing - Look at my other post for details on this
 
localparam N = 18;
 
reg [N-1:0]count;
 
always @ (posedge clock or posedge reset)
 begin
  if (reset)
   count <= 0;
  else
   count <= count + 1;
 end
 
reg [6:0]sseg;
reg [3:0]an_temp;
reg reg_dp;
always @ (*)
 begin
  case(count[N-1:N-2])
    
   2'b00 : 
    begin
     sseg = reg_d0;
     an_temp = 4'b1110;
     reg_dp = 1'b1;
    end
    
   2'b01:
    begin
     sseg = reg_d1;
     an_temp = 4'b1101;
     reg_dp = 1'b0;
    end
    
   2'b10:
    begin
     sseg = reg_d2;
     an_temp = 4'b1011;
     reg_dp = 1'b1;
    end
     
   2'b11:
    begin
     sseg = reg_d3;
     an_temp = 4'b0111;
     reg_dp = 1'b0;
    end
  endcase
 end
assign an = an_temp;
 
reg [6:0] sseg_temp; 
always @ (*)
 begin
  case(sseg)
   4'd0 : sseg_temp = 7'b1000000;
   4'd1 : sseg_temp = 7'b1111001;
   4'd2 : sseg_temp = 7'b0100100;
   4'd3 : sseg_temp = 7'b0110000;
   4'd4 : sseg_temp = 7'b0011001;
   4'd5 : sseg_temp = 7'b0010010;
   4'd6 : sseg_temp = 7'b0000010;
   4'd7 : sseg_temp = 7'b1111000;
   4'd8 : sseg_temp = 7'b0000000;
   4'd9 : sseg_temp = 7'b0010000;
   default : sseg_temp = 7'b0111111; //dash
  endcase
 end
assign {g, f, e, d, c, b, a} = sseg_temp; 
assign dp = reg_dp;

endmodule
 

You compile the stopwatch code as the top level file. The ports of the module become the pins used on the FPGA.

- - - Updated - - -

btw this:
Code: 
 else if(ticker == 5000000) //if it reaches the desired max value reset it
  ticker <= 0;
does not generate a 0.1 sec tick.

you are counting 5000001 times instead of 5000000 times.

I find it somewhat perplexing that so many post code with that simple error.
 
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can you give assistance on how to do mapping of ports and pins.. I guess pins are names as HEX0, HEX 1 etc you mean to say i should assign or equate these ports to pins

- - - Updated - - -

Do I need to map

output a, b, c, d, e, f, g, dp,
output [3:0] an

to my pin plannar
 

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