Error in Verilog - Calling Other Files in Same Project

Thread starter testing test
Start date Nov 21, 2010

Status: Not open for further replies.

Nov 21, 2010

testing test

Member level 3

Hello,

I am writing code for the main file of my project which makes use of other files within the same project. I am trying to call some files into my main project file with the following commands:

Code:

                Byte_Sub bs0(BS,Cipher_Text);
                Shift_Rows sr0(SR,BS);

The error coming up is

Code:

Undefined variable: Byte_Sub.
near "bs0". syntax error, unexpected "IDENTIFIER"
Undefined variable: Shift+Rows.

Please look into the issue and suggest any solutions.

Thank you.

Status: Not open for further replies.

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Error in Verilog - Calling Other Files in Same Project

testing test

Member level 3

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