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Error in Verilog - Calling Other Files in Same Project

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testing test

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Hello,

I am writing code for the main file of my project which makes use of other files within the same project. I am trying to call some files into my main project file with the following commands:

Code: 
                Byte_Sub bs0(BS,Cipher_Text);
                Shift_Rows sr0(SR,BS);

The error coming up is

Code: 
Undefined variable: Byte_Sub.
near "bs0". syntax error, unexpected "IDENTIFIER"
Undefined variable: Shift+Rows.

Please look into the issue and suggest any solutions.

Thank you.
 

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