error in post place and route simulation

[sarmad88]

help me please
my project in VHDL code use the Fixed point package by David Bishop and i use the spartan3E board and when make post place and route simulation the below error occur:

ERROR:HDLCompiler:1316 - "G:/project/VHDL/final_with_PAR-simulation/netgen/par/main_timesim.vhd" Line 28014: Index value <-16> is out of range [0:2147483647] of array <std_logic_vector>
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit main in library work failed

and this error occur in the line :
signal operation_comp_sum30 : STD_LOGIC_VECTOR ( 13 downto -16 );

and i d'not know how can solve this error please any one help me to solve this error

 

[sarmad88]

help me please
my project in VHDL code use the Fixed point package by David Bishop and i use the spartan3E board and when make post place and route simulation the below error occur:

ERROR:HDLCompiler:1316 - "G:/project/VHDL/final_with_PAR-simulation/netgen/par/main_timesim.vhd" Line 28014: Index value <-16> is out of range [0:2147483647] of array <std_logic_vector>
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit main in library work failed

and this error occur in the line :
signal operation_comp_sum30 : STD_LOGIC_VECTOR ( 13 downto -16 );

and i d'not know how can solve this error please any one help me to solve this error

Hi,

Modify the line as below in main_timesim.vhd

signal operation_comp_sum30 : STD_LOGIC_VECTOR ( 13 downto -16 );

to

signal operation_comp_sum30 : STD_LOGIC_VECTOR1 ( 13 downto -16 );

Thanks.