micro designer
Junior Member level 2
hi ,
I have used the verilog-A model of opamp in cadence ahdl library as shown in the file View attachment code.txt. It models the dominant pole of the opamp and slewing limitation.
following values were taken for the opamp parameters :
open loop gain = 1000, unity gain frequency = 50 MHz shown here the schematic
I have done AC analysis by providing sinusoidal signal with ac mag=0.2 to the inverting terminal of opamp. ac plots are here
. but the plot shows the ugf to be 10MHz and gain around 250 which is not matching with the values taken. What could be the reason for this? is the code shown is right as far as the modeling of dominant pole concerned.
thanks
I have used the verilog-A model of opamp in cadence ahdl library as shown in the file View attachment code.txt. It models the dominant pole of the opamp and slewing limitation.
following values were taken for the opamp parameters :
open loop gain = 1000, unity gain frequency = 50 MHz shown here the schematic
I have done AC analysis by providing sinusoidal signal with ac mag=0.2 to the inverting terminal of opamp. ac plots are here
. but the plot shows the ugf to be 10MHz and gain around 250 which is not matching with the values taken. What could be the reason for this? is the code shown is right as far as the modeling of dominant pole concerned.thanks
