library IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity column_counter_tb is
end;
architecture behavior of column_counter_tb is
--Inputs
signal rst: std_logic:='1';
signal clk: std_logic:='0';
--Outputs
signal col_out: std_logic_vector(3 downto 0);;
-- clock period definitions
constant clkperiod : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.column_counter port map(
col_out => col_out,
rst => rst,
clk => clk);
-- Clock process definitions
clkprocess :process
begin
clk <= '1';
wait for clkperiod/2;
clk <= '0';
wait for clkperiod/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 70 ns;
rst <= '0';
wait for 140 ns;
rst <= '1';
wait for 200 ns;
rst <= '0';
wait;
end process;
end;