Error in generating netlist according to Xilinx EDK tutorial

Status
Not open for further replies.

raylay

Member level 2
Joined
Mar 20, 2004
Messages
43
Helped
5
Reputation
10
Reaction score
4
Trophy points
1,288
Location
Beijing
Activity points
150
Xilinx EDK help

I follow the EDK6.1 tutor.when i generate netlist, the error come out,
----------------------------------------------------------------

(Console Log)
Project Opened.
Command bash -c "cd /xygdrive/e/temp/XilinxReferenceSystems/plb_ssp3_v1_00_a/; make -f system.make netlist; exit;" Started...
*********************************************
Creating system netlist for hardware specification..
*********************************************
platgen -p xc2vp7fg456-6 -lang vhdl -st xst system.mhs
Release 6.1i - platgen EDK_G.12
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
ERROR:MDT - Invalid target speed '-6'
ERROR:MDT - platgen failed with errors!
make: *** [implementation/system.ngc] Error 2
Done.

-------------------------------------------------------------------------
but I couldn't modify target speed option!

Thank you for your advise!
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…