[SOLVED] error in compile hdl program

[imnimn]

library ieee;
use ieee.std_logic_1164.all;
entity usr is 
port(clk,srsi,slsi:in bit;
s :in bit_vector(1 downto 0);
I: in bit_vector(3 downto 0);
A: out bit_vector(3 downto 0));
end;
architecture universal_shift_register of usr is
component mux is    
port(a0,a1,a2,a3:in bit; 
S: in bit_vector (1 downto 0); 
f: out bit );
end component;
component D_flip_flop  is port
(clk,d:in bit; 
r: out bit );
end component ;
signal d0:bit;
signal d1:bit;
signal d2:bit;
signal d3:bit;
signal da0:bit;
signal da1:bit;
signal da2:bit;
signal da3:bit;
begin
U0:mux port map(da0,da1,slsi,i(0),s,d0); 
U1:mux port map (da1,da2,da0,i(1),s,d1);
U2:mux port map(da2,da3,da1,i(2),s,d2);
U3:mux port map(da3,srsi,da2,i(3),s,d3);
U4:D_flip_flop  port map(clk,d0,da0);
--U5:D_flip_flop  port map(clk,d1,da1);
--U6:D_flip_flop  port map(clk,d2,da2);
--U7:D_flip_flop  port map(clk,d3,da3);
A(3)<=da3;
A(2)<=da2;
A(1)<=da1;
A(0)<=da0;
end;

library ieee;
use ieee.std_logic_1164.all;
entity mux is    
port(a0,a1,a2,a3:in bit; 
S: in bit_vector (1 downto 0); 
f: out bit );
end;
architecture mux4_1 of mux is
begin 
process (S)
begin 
case S is
 when "00" =>
  f <= a0;
 when "01" =>
  f <= a1;
 when "10" =>
  f <= a2;
 when "11" =>
  f <= a3;
 end case;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity D_flip_flop is port
(clk,d:in bit; 
r: out bit );
end;
architecture ff of D_flip_flop  is
begin 
process (clk,d)
begin 
if(clk'event and clk<= '1')then
r<=d;
end if;
end process;
end;

---------- Post added at 10:50 ---------- Previous post was at 10:42 ----------

i want your help

 

[TrickyDicky]

whats the error?

 

[imnimn]

the compiler said that he cn't make the edge by combining clk'event and another thing "i don't know why"

 

[TrickyDicky]

change this:
if(clk'event and clk<= '1')then

to this:

if(clk'event and clk = '1')then

 

[imnimn]

at the begining i wrote instead of D_flip_flop dff and he wrote to me that i didn't put any thing on f1 in dff although i put da0
then i saw warning that dff won't be seen
then i changed it

---------- Post added at 14:27 ---------- Previous post was at 14:27 ----------

thank you
very much

---------- Post added at 15:03 ---------- Previous post was at 14:27 ----------

i did what you told me but this error appear until now appear

Error: Port "f1" does not exist in primitive "dff" of instance "U4"

---------- Post added at 15:06 ---------- Previous post was at 15:03 ----------

it's done now thank you very much i won't forget that TrickyDicky