ERROR in cadence while checking DRC rules

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S_J_K

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hello everyone!
i have designed the symbol view of cmos amplifier and now i am creating the layout of it. While checking the DRC rules , error named "tap area" is being observed. Can anyone help me in resolving this error?

regards
SJK
 

It is hard to say anything without more details but "tap area" is related to well/substrate connections. Probably You have not enough or proper bulk connections.
 

#Dominik
I have exported the schematic for layout. Do i have to make layout myself?
 

An auto-generated layout probably has no taps, hence
tap-density type errors. It's telling you "OK, your turn
to step in and finish the job" most likely.
 

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