Hi All,
I want to estimate the power using a VCD I dump directly from my testbench. The commands I use for dumping the VCD are:
I use the following Cadence RTL compiler command in my synthesis script (after elaborate and before synthesize)
I receive the following error:
I have included the testbench file Top_tb.v as well as synthesizable top module Top.v in the read location for the tool to find (../rtl/).
Can anyone help me with this? I will greatly appreciate it.
Thank you!