Error in Cadence RTL Compiler when estimating Power using VCD

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saunaksaha

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Hi All,

I want to estimate the power using a VCD I dump directly from my testbench. The commands I use for dumping the VCD are:

$dumpfile("OneExample.vcd");
$dumpvars(0, Top_tb.CyNAPSE);


(testbench file is Top_tb and the module instantiated in it is CyNAPSE of type Top. Top is the top module included in the synthesizable RTL)
I use the following Cadence RTL compiler command in my synthesis script (after elaborate and before synthesize)

read_vcd -vcd_module Top_tb -module Top -static ../rtl/OneExample.vcd

I receive the following error:

I have included the testbench file Top_tb.v as well as synthesizable top module Top.v in the read location for the tool to find (../rtl/).
Can anyone help me with this? I will greatly appreciate it.


Thank you!
 
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your vcd file is corrupted or incomplete. try generating a small file first, with only a few clock cycles of sim time, and see if it works.
 

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