Dec 3, 2015 #1 H hulk789 Junior Member level 3 Joined Jul 18, 2015 Messages 27 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 211 Code: entity concurr is port (a:out bit;b:in bit); end concurr; architecture Behavioral of concurr is signal z,t:bit; begin a<=postponed b after 10ns; end Behavioral; Why there is error in the following line a<=postponed b after 10ns;
Code: entity concurr is port (a:out bit;b:in bit); end concurr; architecture Behavioral of concurr is signal z,t:bit; begin a<=postponed b after 10ns; end Behavioral; Why there is error in the following line a<=postponed b after 10ns;
Dec 3, 2015 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,478 Helped 14,756 Reputation 29,794 Reaction score 14,120 Trophy points 1,393 Location Bochum, Germany Activity points 298,338 Because it's no legal VHDL syntax. Postponed would be inserted before a concurrent assignment. Presume you know that it's only relevant in simulation. Code: postponed a<=b;
Because it's no legal VHDL syntax. Postponed would be inserted before a concurrent assignment. Presume you know that it's only relevant in simulation. Code: postponed a<=b;