i was trying to synthesize my project using design_analyzer and analyzing step works correctly, but the elaborating steps generates this message:
"ERROR: in design 'multiplier', connectionto port 'a' of instance 'half_multiplier_0' is too narrow. (DDX-2)
can anyone help me please to resolve this problem,
the ports are diffrent sizes but i m using just the bits that i need:
example
suppose that a : std_logic_vectot (5 downto 0)
an b : std_logic_vector (10 downto 0),
i put in my vhdl code:
a => b(5 downto 0),
the functional simulation (Modelsim) before the synthezis works correctly, the pbl is during the synthezis
Other than make the bus widths the same, no.
Download a free synthesizer like Xilinx ISE and test it out. Maybe it's just DC that's the problem. Weird.