Error generated by Design_analyzer from synopsys (DDX-2)

[Aminos]

i was trying to synthesize my project using design_analyzer and analyzing step works correctly, but the elaborating steps generates this message:
"ERROR: in design 'multiplier', connectionto port 'a' of instance 'half_multiplier_0' is too narrow. (DDX-2)

can anyone help me please to resolve this problem,

thank you in advance,

Aminos

 

[gliss]

Are the ports different sizes? Post the HDL that you're tyring to synthesize.

 

[Aminos]

the ports are diffrent sizes but i m using just the bits that i need:
example
suppose that a : std_logic_vectot (5 downto 0)
an b : std_logic_vector (10 downto 0),
i put in my vhdl code:
a => b(5 downto 0),

the functional simulation (Modelsim) before the synthezis works correctly, the pbl is during the synthezis

 

[gliss]

a => b(5 downto 0)

should be:

a <= b( 5 downto 0);

 

[Aminos]

yes i know that but this signal is an instanciation of component:
half_multiplier:multiplier
port map(
a => b (5 downto 0),
.
.
.
);

 

[gliss]

I don't know if all synthesizers can handle subelement associations. Can you try another synthesizer?

 

[Aminos]

unfortunatly no, cause we re supposed to work just on this ynthesizers, do you have any other idea to avoid this problem?

 

[gliss]

Other than make the bus widths the same, no.
Download a free synthesizer like Xilinx ISE and test it out. Maybe it's just DC that's the problem. Weird.