[SOLVED] "ERROR: [Common 17-165] Too many positional options when parsing

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rafimiet

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I try to simulate a design with the test bench as follows:
Code VHDL - [expand]
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
 
ENTITY fsm_tbw IS
END fsm_tbw;
 
ARCHITECTURE behavior OF fsm_tbw IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT FSM_all
    PORT(
         rst : IN  std_logic;
         clk : IN  std_logic;
         i : IN  std_logic_vector(7 downto 0);
            out_en : OUT std_logic;
         y : OUT  std_logic_vector(10 downto 0)
        );
    END COMPONENT;
    
 
   --Inputs
   signal rst,out_en : std_logic := '0';
   signal clk,endoffile : std_logic := '0';
   signal i : std_logic_vector(7 downto 0) := (others => '0');
 
    --Outputs
   signal y : std_logic_vector(10 downto 0);
 
   -- Clock period definitions
   constant clk_period : time := 10 ns;
    
    -- TEXT FILE --
    FILE g: TEXT OPEN WRITE_MODE IS "trans.txt";
    FILE f: TEXT OPEN READ_MODE IS "orig.txt";
 
 
BEGIN
 mapping: FSM_all port map (rst, clk,i,out_en,y);
   -- Clock process definitions
rst <= '0';
clk <= NOT clk AFTER 10ns;
 
 
   -- Stimulus process
   reading: process
        VARIABLE l: LINE;
        VARIABLE good_value : BOOLEAN;
        VARIABLE pixl1 : INTEGER RANGE 0 TO 255;
   begin    
        wait until clk = '1' and clk'event;
        if (not endfile(f)) then
            READLINE(f,l);
            READ(l,pixl1,good_value);
            i <= std_logic_vector(to_signed(pixl1,8));
        else
            endoffile <='1';         --set signal to tell end of file read file is reached.
        end if;
    end process reading;
    writing: process
        VARIABLE m: LINE;
        VARIABLE good_value : BOOLEAN;
        VARIABLE pixl3 : INTEGER RANGE 0 TO 255;
        variable count : INTEGER RANGE 0 TO 255;
   begin    
        wait until clk = '1' and clk'event;
        if out_en = '1' then
            if count <= 262144 then
                pixl3 := to_integer(signed(y));
                WRITE(m,pixl3);
                WRITELINE(g,m);         --set signal to tell end of file read file is reached.
                count := count + 1;
            end if;
        end if;
    end process writing;
    
 
END behavior;

I get the following errors:
The same testbench works fine in ISIM (used in ISE 14.4). Can anybody tell me what to do?
 

ERROR: File orig.txt could not be opened
on HDL file D:/Local Disk/PHD_WORK/xilinx_projects/vivado_learning_project/vivado_learning_project.srcs/sim_1/new/fsm_tbw.vhd line 67
Click to expand...

Are you sure Vivado can access that file?


I do something like...
Code: 
use ieee.std_logic_textio.all;
use STD.textio.all;
.
.
        file rx_data : text ;         -- Declare read file variable 
.
.
.

        -- Open file for reading              
        file_open(rx_data, "C:\Work\elog\fpga_a7\sources\sim\ddd_elog2host_data.txt", read_mode);
 

"ERROR: [Common 17-165] Too many positional options when parsing 'projects/vivado_learning_project/vivado_learning_project.hw/webtalk/labtool_webtalk.l..."
(file "D:/Local" line 1)
Click to expand...

This error comes when you are instatiating a component using positional association and are trying to connect more things than exist in the component (please use named association to avoid this).

The other indicates vivado cannot open orig.txt
 

Tricky...please use named association to avoid this
Click to expand...
Can you please elaborate on this wrt above code?
 

The path it points to is obscured. So I dont the problem is in the testbench

as for named association:

Code VHDL - [expand]
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mapping: FSM_all port map (
  rst => rst, 
  clk => clk,
  i => i,
  out_en => out_en,
  y => y);
 

It looks to me like all the errors are mostly caused by running in a directory with a space in the name.
D:/Local<space>Disk/PHD_WORK/

That space in the name is breaking the auto generated scripts created when running a simulation from the Vivado GUI. This kind of stuff is why I only use the GUI to generate a script to find all the simulation code for the IPs and then write my own simulation script.
 
Both the errors have been rectified by
1) Avoiding spaces in the absolute path of the project as rightly said by ads-ee
That space in the name is breaking the auto generated scripts created when running a simulation from the Vivado GUI.
Click to expand...
2) By providing the absolute path of the text file. In ISE, I was placing the file in project's current directory, and then just providing the name only. But in vivado, we need to provide the whole path, otherwise, vivado deletes the file on its own.
 

rafimiet said:
2) By providing the absolute path of the text file. In ISE, I was placing the file in project's current directory, and then just providing the name only. But in vivado, we need to provide the whole path, otherwise, vivado deletes the file on its own.
Click to expand...

It might be that the simulation is running in a different folder than you expect. This is why I always like to run simulations manually (although I have never used the vivado simulator, I never use internal projects in Modelsim or ActiveHDL)
 

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