Error (10500)

[shahrilmajid]

Can anyone help me? I am trying to use concurrent statements in this code. Is there anything wrong with ";" that I use in the code ?

 

[barry]

Not sure what’s wrong with your code; it might be that you’re using the WHEN-ELSE inside a process; I’ve never done that and don’t see a reason to. But I would use a CASE statement for your application.

 

[FvM]

Would you mind to post .vhd text instead of a screenshot, so we can check the actual code?

Error is to use conditional assignment (to be used in concurrent code) in a process (sequential code). Use a case construct or "if elsif else" instead.

 

[shahrilmajid]

Would you mind to post .vhd text instead of a screenshot, so we can check the actual code?

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity whenelse is
port (in_A, in_B : in std_logic_vector (7 downto 0);
     opcode : in std_logic_vector (1 downto 0);
     out_y : out std_logic_vector (7 downto 0);
     carry : out std_logic);
    end whenelse;
    
architecture beh of whenelse is
signal tmp    :    std_logic_vector(8 downto 0);
    begin
        process    (opcode)
            begin
            --start code
            tmp <=        ("0" & in_A) + ("0" & in_B)   when opcode = "00"   else
                        ("0" & in_A) - ("0" & in_B)   when opcode = "01"   else
                        ("0" & in_A) and ("0" & in_B) when opcode = "10"   else
                        ("0" & in_A) or ("0" & in_B)  when opcode = "11" ;
            end process;
out_y <= tmp (7 downto 0);
carry <= tmp (8);
end beh;

--- Updated Nov 6, 2021 ---

Would you mind to post .vhd text instead of a screenshot, so we can check the actual code?

Error is to use conditional assignment (to be used in concurrent code) in a process (sequential code). Use a case construct or "if elsif else" instead.

Is it possible for me to use concurrent assignment with "when" "else" statemen as in https://insights.sigasi.com/tech/signal-assignments-vhdl-withselect-whenelse-and-case/

 

[FvM]

Or simply remove the unneccessary process:

architecture beh of whenelse is
signal tmp    :    std_logic_vector(8 downto 0);
    begin
--        process    (opcode)
--            begin
            --start code
            tmp <=        ("0" & in_A) + ("0" & in_B)   when opcode = "00"   else
                        ("0" & in_A) - ("0" & in_B)   when opcode = "01"   else
                        ("0" & in_A) and ("0" & in_B) when opcode = "10"   else
                        ("0" & in_A) or ("0" & in_B)  when opcode = "11" ;
--            end process;
out_y <= tmp (7 downto 0);
carry <= tmp (8);
end beh;

 

[shahrilmajid]

Or simply remove the unneccessary process:

architecture beh of whenelse is
signal tmp    :    std_logic_vector(8 downto 0);
    begin
--        process    (opcode)
--            begin
            --start code
            tmp <=        ("0" & in_A) + ("0" & in_B)   when opcode = "00"   else
                        ("0" & in_A) - ("0" & in_B)   when opcode = "01"   else
                        ("0" & in_A) and ("0" & in_B) when opcode = "10"   else
                        ("0" & in_A) or ("0" & in_B)  when opcode = "11" ;
--            end process;
out_y <= tmp (7 downto 0);
carry <= tmp (8);
end beh;

Thank you. I learned something today from you today.

 

[TrickyDicky]

When-else syntax is only valid inside a process from VHDL 2008 onwards.

 

[FvM]

When-else syntax is only valid inside a process from VHDL 2008 onwards.

Thanks for mentioning. It's not yet supported by Quartus in VHDL2008 setting, at least until V20.1.

 

[TrickyDicky]

IIRC, Only Prime pro was getting 2008 updates. Prime lite is stuck with what they implemented over 10 years ago (which wasnt a lot).