shahrilmajid
Newbie level 4
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity lab1 is
port (in_A, in_B : in std_logic_vector (7 downto 0);
opcode : in std_logic_vector (1 downto 0);
out_y : out std_logic_vector (7 downto 0);
carry : out std_logic);
end lab1;
architecture beh of lab1 is signal tmp :
std_logic_vector(8 downto 0);
begin
process (opcode)
begin
if opcode = "00" then --cond1
tmp <=("0" & in_A) + ("0" & in_B);
else if opcode = "01" then --cond2
tmp <=("0" & in_A) - ("0" & in_B);
else if opcode = "10" then --cond2
tmp <=("0" & in_A) and ("0" & in_B);
else
tmp <=("0" & in_A) or ("0" & in_B);
end if;
end process;
out_y <= tmp (7 downto 0);
carry <= tmp (8);
end beh;
could anyone help me.. i am stuck when this error message