Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package ALU is function addition (A,B: bit_vector) return bit_vector; function subtraction (A,B: bit_vector) return bit_vector; function multiplication (A,B: bit_vector) return bit_vector; function pass_A (A: bit_vector) return bit_vector; function Logical_AND (A,B: bit_vector) return bit_vector; function Logical_OR (A,B: bit_vector) return bit_vector; function shift_R (A: bit_vector) return bit_vector; function shift_L (A: bit_vector) return bit_vector; end ALU; package body ALU is function addition (A,B: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := A+B; return Y; end function; function subtraction (A,B: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := A-B; return Y; end function; function multiplication (A,B: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := A*B; return Y; end function; function pass_A (A: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := A; return Y; end function; function Logical_AND (A,B: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := A AND B; return Y; end function; function Logical_OR (A,B: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := A OR B; return Y; end function; function shift_R (A: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := '0'& Y(15 downto 1) ; return Y; end function; function shift_L (A: bit_vector) return bit_vector is variable Y: bit_vector (15 downto 0); begin Y := Y(14 downto 0)&"0"; return Y; end function; end package body;
what is the error in that code ???Error (10327): VHDL error at ALU.vhd(21): can't determine definition of operator ""+"" -- found 0 possible definitions
not being a VHDL expert,... doesn't the unconstrained width for the inputs require an unconstrained variable instead of variable Y: bit_vector (15 downto 0);?
Seems to me the variable Y is defining the input (and output) bit widths, which I don't think flies with VHDL.
Figured as much, but didn't think setting the variable width was a good idea as it forces the inputs to only be 16-bits, if that was the case then just make the inputs 16-bits.It will work just fine - as long as both inputs are also 16 bits.
Y should be constained to
std_logic_vector(maximum(a'length, b'length)-1 downto 0);
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package ALU is function addition (A,B: std_logic_vector) return std_logic_vector; function subtraction (A,B: std_logic_vector) return std_logic_vector; function multiplication (A,B: std_logic_vector) return std_logic_vector; function pass_A (A: std_logic_vector) return std_logic_vector; function Logical_AND (A,B: std_logic_vector) return std_logic_vector; function Logical_OR (A,B: std_logic_vector) return std_logic_vector; function shift_R (A: std_logic_vector) return std_logic_vector; function shift_L (A: std_logic_vector) return std_logic_vector; end ALU; package body ALU is function addition (A,B: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := A+B; return Y; end function; function subtraction (A,B: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := A-B; return Y; end function; function multiplication (A,B: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := A*B; return Y; end function; function pass_A (A: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := A; return Y; end function; function Logical_AND (A,B: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := A AND B; return Y; end function; function Logical_OR (A,B: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := A OR B; return Y; end function; function shift_R (A: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := '0'& Y(15 downto 1) ; return Y; end function; function shift_L (A: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := Y(14 downto 0)&"0"; return Y; end function; end package body;
Code VHDL - [expand] 1 2 3 4 5 6 function addition (A,B: std_logic_vector) return std_logic_vector is variable Y: unsigned (15 downto 0); begin Y := unsigned(A)+unsigned(B); return std_logic_vector(Y); end function;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std_unsigned.all; -- note this is a new package that handles std_logic_vector as numbers package ALU is function addition (A,B: std_logic_vector) return std_logic_vector; end ALU; package body ALU is function addition (A,B: std_logic_vector) return std_logic_vector is variable Y: std_logic_vector (15 downto 0); begin Y := A+B; return Y; end function; end package body;
It does supported the quoted VHDL 2008 libraries.I am using Quartus Prime Lite Edition 15.1.0.185 software. Is it Okey?
It does supported the quoted VHDL 2008 libraries.
I think that while Quartus 15 does have some VHDL 2008 support, the new libraries have to be added manually, and be the '93 compatible ones.
Right, I was mislead by the fact that the libraries are in the quartus ieee/2008 directory, but that apparently means nothing. Needless to say that I have absolutely no use for this stuff anyway.I think that while Quartus 15 does have some VHDL 2008 support, the new libraries have to be added manually, and be the '93 compatible ones.
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