-- junk.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity cpld is
port (
dir: in STD_LOGIC;
a_bus: inout STD_LOGIC;
b_bus: inout STD_LOGIC
);
end cpld;
architecture Structure of cpld is
signal i_a_in: STD_LOGIC;
signal i_a_out: STD_LOGIC;
signal i_b_in: STD_LOGIC;
signal i_b_out: STD_LOGIC;
component G_BIDIR Port (
I : in std_logic;
OE : in std_logic;
O : inout std_logic;
FBK : out std_logic );
end component;
begin
A_BUS: G_BIDIR port map( I => i_a_out, OE => dir , O => a_bus, FBK => i_a_in );
B_BUS: G_BIDIR port map( I => i_b_out, OE => not dir, O => b_bus, FBK => i_b_in );
i_a_out <= i_b_in;
i_b_out <= i_a_in;
end Structure;
---------------------------
library ieee;
use ieee.std_logic_1164.all;
entity G_BIDIR is Port (
I : in std_logic;
OE : in std_logic;
O : inout std_logic;
FBK : out std_logic );
end G_BIDIR;
architecture behavioral of G_BIDIR is
begin
O <= I when OE='1' else 'Z';
FBK <= O;
end behavioral;