Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Erroe AMP in DC DC Converter Design

Status
Not open for further replies.

schwang1970

Member level 2
Joined
Mar 11, 2005
Messages
48
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,639
Hi, everybody
Did anyone can explain why the error amp. output in dc dc converter need a clamp
circuit ?? How to design the clamp circuit?
Thank you !
 

VVV

Advanced Member level 5
Joined
Nov 26, 2004
Messages
1,582
Helped
384
Reputation
768
Reaction score
88
Trophy points
1,328
Activity points
19,971
Perhaps you are referring to the duty-cycle clamp?
Essentially, limit the duty-cycle, such that no matter what the error amp output does, the maximum duty-cycle is never exceeded.
See the datasheet of the PWM chip for the correct method to clamp the duty-cycle.
 

schwang1970

Member level 2
Joined
Mar 11, 2005
Messages
48
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,639
If I have a voltage(vref) in postive input of error pamp and a feedback voltage(vfb) from the dc converter output to the negative input of err opamp. The dc converter optput initial is zero.When in closed-loop simulation what is the right error opamp output will to be??
 

Davood Amerion

Advanced Member level 2
Joined
Mar 1, 2005
Messages
584
Helped
116
Reputation
232
Reaction score
24
Trophy points
1,298
Location
Persia
Activity points
6,345
in this case you can use inverting-amplifier (with use of op-amp).
and change negative input voltage to positive one.
 

VVV

Advanced Member level 5
Joined
Nov 26, 2004
Messages
1,582
Helped
384
Reputation
768
Reaction score
88
Trophy points
1,328
Activity points
19,971
The output voltage of the error amp should be initialized to that voltage that produces the correct duty-cycle for the desired output voltage and current, at the given input voltage.

For example, if for a 5V / 1A output and an input voltage of 12V you need a duty-cycle of 0.475 and you know that to obtain that you need 3.451V from the error amp output, then you initialize it to 3.451V.
 

schwang1970

Member level 2
Joined
Mar 11, 2005
Messages
48
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,639
I still have two questions
(1) The error opamp DC gain is 1000 and the error opamp output is 1000*(vip-vin)
if the converter output initial is zero, then the error opamp output is saturation
to VDD.Only when the error opamp positive and negative input are very close
and the error opamp output are not saturated to VDD.That is need to clamp the
error opamp output to the desired voltage.Right??
(2) If the DC converter input range is 1.8~3.6 ,output is 3.0. How to set the desired
output voltage of error opamp. Because it has buck and boost opreration.

Thank you!
 

VVV

Advanced Member level 5
Joined
Nov 26, 2004
Messages
1,582
Helped
384
Reputation
768
Reaction score
88
Trophy points
1,328
Activity points
19,971
1. The output voltage should also be initialized to the steady-state value, in order to avoid the saturation of the error amp.
The error amp output is clamped to such a value that will produce the maximum allowable duty-cycle. This maximum is based on other considerations: driver type, converter type (a buck can take 100%, but not a forward), etc.

2. You should run the simulation for one input voltage at a time. You then calculate the required duty-cycle for that particular voltage and initialize the error amp output to the value that will produce that duty-cycle.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top