Whitebird
Newbie level 2
Hi everybody,
In my design I use an EP1C3T100C8N cyclone which gets configured from an EPCS1 serial device.
EPCS1 is programmed from an external microcontroller that gets the data stream from a PC which reads an .hex file (generated with quartus II).
The configuration device seems to be correctly programmed because during verification, every byte of data reads OK.
But the FPGA cannot configure from the device. It is toggling DCLK, I can see what seems to be the first 128 bytes of configuration data going out at DATA pin (of EPCS1 device), but after that, the cycle repeats indefinitely.
CONF_DONE never goes high but nSTATUS is toggling which probably means an error is detected...
I know exactly when the cycle repeats:
The first 128 bytes of my configuration file are:
FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6ADEFF4000682F0300 6ADEFF4000682F03006ADEFF4000682F030000FFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFF44555444555574755777755776755676 75577765566665563625522225D2E3551A1551111551111551 111551
After receiving the first 44 bytes of data, FPGA switch nCS back to high level and DCLK stops to run.
It seems there may be something wrong in the first 44 bytes (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6ADEFF4000682F030 06ADEFF4000682F03006ADEFF4000682F030000)
Can you please help me?
Whitebird
In my design I use an EP1C3T100C8N cyclone which gets configured from an EPCS1 serial device.
EPCS1 is programmed from an external microcontroller that gets the data stream from a PC which reads an .hex file (generated with quartus II).
The configuration device seems to be correctly programmed because during verification, every byte of data reads OK.
But the FPGA cannot configure from the device. It is toggling DCLK, I can see what seems to be the first 128 bytes of configuration data going out at DATA pin (of EPCS1 device), but after that, the cycle repeats indefinitely.
CONF_DONE never goes high but nSTATUS is toggling which probably means an error is detected...
I know exactly when the cycle repeats:
The first 128 bytes of my configuration file are:
FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6ADEFF4000682F0300 6ADEFF4000682F03006ADEFF4000682F030000FFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFF44555444555574755777755776755676 75577765566665563625522225D2E3551A1551111551111551 111551
After receiving the first 44 bytes of data, FPGA switch nCS back to high level and DCLK stops to run.
It seems there may be something wrong in the first 44 bytes (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6ADEFF4000682F030 06ADEFF4000682F03006ADEFF4000682F030000)
Can you please help me?
Whitebird
