Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Enquiry about the tool Encounter

Status
Not open for further replies.

aditya1579

Member level 2
Member level 2
Joined
Jan 2, 2013
Messages
47
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Visit site
Activity points
1,624
Hi All,

During the standard cell placement, there are no real routes. Then how does the tool do the timing ?

Is it based on some estimation technique like Steiner routes etc ?

Aditya
 

the timing is done through estimated parasitic depending on the fanout of the gates. The cell size is available, pin_cap on the nets is there and parasitic tables are available. It is just an estimate.
 

During the placement, the tool does a non-drc clean global routing, called as trial-route, to help the parasitic estimation.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top