Encounter RC Compiler - synthesize to vhdl file

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sambhav007

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Hi,

I am using Encounter RC compiler to synthesize my verilog/vhdl files into gate-level netlists, using a standard cell library.

However, the logic synthesis process only creates a synthesized .v file (output file)
Is it possible to generate a .vhd synthesized file using RTL compiler?

Thanks,
Sambhav
 

this is an analog IC design forum, why post here? Most synthesizers generate (structural) verilog since most place and route tool only accept verilog, you can always use import>verilog to generate a schematic to review the result
 
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Sorry for posting in the wrong forum. How do i move it to the correct forum?

By the way, the problem arises when I need to simulate the synthesized design (with gate delays).
I have a vhdl design and testbench (vhdl). And since after synthesis i get a verilog file, i cannot simulate that file using my vhdl testbench.
 

RTL compiler can only write out a design or subdesign in Verilog.

---------- Post added at 16:17 ---------- Previous post was at 16:12 ----------

What are you using for simulation? I use NCSim. With NCLaunch its no problem to compile a Verilog design with a VHDL testbench and use them together.
 

Same for questa/modelsim, there is no problem mixing the two (you still need to read the manual on how to do it exactly)
 

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