Encounter LVS error in Calibre

[Chenxin Jiang]

Hi there, I was running Calibre LVS check for my design but I encounter some problem. When I run LVS check on module level, which means check each module individually, there is no error. But after I run top level design check, which contains all the submodules, it reports many LVS error in the sub-module. The problems contains net and instance mismatch. My problem is that why the pre-checked module still has error in top level check. I use LVS rule suplied by TSMC and I use netlist file exported from Innovus. I use v2lvs to transform the netlist into spice form, I first transform sub-modules and then include them in my top level spice file. Could you please give me some idea? Thanks!

 

[ThisIsNotSam]

You can have perfectly correct modules and still make mistakes in top-level connections. LVS would show these mistakes somewhere, not necessarily on the top level when you include everything. Debug debug debug. Consider adding one block at a time if possible.