Re: Spice simulations
What kind of errors are you getting? Is it a syntax error or is it a problem like
convergence error? If you can post your errors (typically found in your *.out file),
I might be able to help out.
There are two things that I see but I don't know if they are the problem
without seeing your *out file.
1. I see that the capacitor C0 is shorted C0 GND GND 2.8fF
there is nothing wrong with shorting it out (it just makes the capacitor voltage = 0
for all time) but I don't know if all simulators like shorting of components.
2. Since this circuit has purely capacitive loads, there is no dc path to ground
unless the fets have some kind of dc path to ground.
If there is no dc path to ground (as in 2.) then PSpice will not be able to compute
the operating points (bias points in the .op analysis) and will quit before doing the
rest of your simulation. The solution is then to put large resistors across the caps,
for example, 10-100Meg.
Also note that PSpice will ignore the first line of your netlist -- it always assumes
that it is the title of the document. If VDD VDD 0 DC 1.22V is the first line
of your netlist, then you would not have any source in your circuit and the
simulation would probably not run.
Give me some more information and I think we will be able to solve your problem.
Cheers,
v_c