Enclosed oscillator simulations problems in PSpice 9.1

[Cyrk]

Hi.

I'm having trouble simulating enclosed oscilator (3-stage crappy design) with PSpice 9.1 (it works just fine on WinSpice and HSpice). Any idea why? Thank you in advance

********************************
VDD VDD 0 DC 1.22V
VGND GND 0 DC 0V

M1000 N1 OUT VDD Vdd pfet w=16.2u l=5.2u
+ ad=10.4328p pd=24.3u as=31.2984p ps=72.9u
M1003 N2 N1 VDD Vdd pfet w=16.2u l=5.2u
+ ad=10.4328p pd=24.3u as=0p ps=0u
M1006 OUT N2 VDD Vdd pfet w=16.2u l=5.2u
+ ad=10.4328p pd=24.3u as=0p ps=0u
M1009 N1 OUT GND Gnd nfet w=6.6u l=5.2u
+ ad=4.0986p pd=12.06u as=12.2958p ps=36.18u
M1012 N2 N1 GND Gnd nfet w=6.6u l=5.2u
+ ad=4.0986p pd=12.06u as=0p ps=0u
M1015 OUT N2 GND Gnd nfet w=6.6u l=5.2u
+ ad=4.0986p pd=12.06u as=0p ps=0u
C0 GND GND 2.8fF
C1 VDD GND 4.1fF
C2 N2 GND 4.8fF
C3 N1 GND 4.8fF
C4 OUT GND 5.1fF


.tran 50p 1000n
.option reltol=1e-5
.probe
.end

 

[v_c]

Re: Spice simulations

What kind of errors are you getting? Is it a syntax error or is it a problem like
convergence error? If you can post your errors (typically found in your *.out file),
I might be able to help out.

There are two things that I see but I don't know if they are the problem
without seeing your *out file.

1. I see that the capacitor C0 is shorted C0 GND GND 2.8fF
there is nothing wrong with shorting it out (it just makes the capacitor voltage = 0
for all time) but I don't know if all simulators like shorting of components.

2. Since this circuit has purely capacitive loads, there is no dc path to ground
unless the fets have some kind of dc path to ground.

If there is no dc path to ground (as in 2.) then PSpice will not be able to compute
the operating points (bias points in the .op analysis) and will quit before doing the
rest of your simulation. The solution is then to put large resistors across the caps,
for example, 10-100Meg.

Also note that PSpice will ignore the first line of your netlist -- it always assumes
that it is the title of the document. If VDD VDD 0 DC 1.22V is the first line
of your netlist, then you would not have any source in your circuit and the
simulation would probably not run.

Give me some more information and I think we will be able to solve your problem.

Cheers,
v_c

 

[Cyrk]

Re: Spice simulations

Actualy I'm not getting any errors, just a flat line instead of oscilations at output. VDD VDD 0 DC 1.22V isn't the first line. I've put large resistors, remover shorted capacitor but I'm still geting flatline.

Plot from winspice:
**broken link removed**
and a plot from PSpice:
**broken link removed**

 

[v_c]

Re: Spice simulations

Looks like the the simulator is finding the bias point of about 0.6V and is sitting there since it knows it must approach this value in the steady state.

What you have to do is to make the system capacitor voltages all start from zero. You do this by using the Use Initial Conditions (UIC) option with the transient analysis statement. Here's the statement

.tran 50p 1000n UIC

Pspice might also want to see two other numbers before the UIC statement. In general, transient statement looks like

.tran <Print Step> <Tstop> <Tstart> <Tstep,max> UIC
so you can put
.tran 50p 1000n 0n 50p UIC
if PSpice gives you errors.

Try it out and see what happens.

Cheers,
v_c

 

[Cyrk]

Spice simulations

It worked! Thank you very much - you're a life saver

 

[v_c]

Re: Spice simulations

That's great! All capacitor voltage initial conditions should start from zero, if you want them from some other voltage just use the IC statement like

C1 1 2 10p IC=4

This will make the capacitor voltage from node 1 to 2 equal to 4V if you use UIC othewise, the simulator will use whatever it computed.

I am glad it worked out for you.

Best regards,
v_c

 

[leoren_tm]

Re: Spice simulations

v_c.. can i ask how to create a pulse supply??

 

[v_c]

Re: Spice simulations

Do you mean a switchmode power supply? These are also known as PWM dc-dc converters. Can you give me some more specifications?

Cheers,
v_c

 

[narccizzo]

Spice simulations

Hi V_C..
maybe you know why the spice model of the 2sc3281 and 2sa1302 doesn't work in the simulation. I have the OrCAD 9.0 version.?

 

[v_c]

Re: Spice simulations

You have to define what "it doesn't work" means. Does this mean that you are getting
errors from the simulator? Is the simulation halting because of convergence errors?
Or maybe the simulation is running fine, but the results are not what you expect or
what the datasheet for the component says. So which one is it ... give me more
information and I might be able to give a useful answer.

Best regards,
\[v_c\]

 

[narccizzo]

Spice simulations

Ok, I'm simulating an audio amplifier. The simulation doesnt have errors the status bar says 100% of the simulation, but there is not a graph screen. If I remove the 2SA1302, 2SC3281, Q2SA1358, Q2SC3421 transistors from the schematic, the simulation works.

 

[v_c]

Re: Spice simulations

If you remove the transistors from the schematic, the simulation runs OK and you get graphs? With the transistors, the simulation runs but you don't get any graphs? I am a little confused ...

 

[narccizzo]

Spice simulations

I´m sorry I didn´t saw the errors because I had no the output window enabled, but with the window I get the error: MODEL Q2SA1302 USED BY Q_Q1 IS UNDEFINED, I don´t why If I changed the transistor by one like MPSA42 everithing is fine. Both transistor has pspice model in the implementation type, If you have a little time you should try to put the Q2SA1302 from the pspice-->jpwrbjt.olb library in one of yours already made analog simulations to see what happends.. thanks.

 

[v_c]

Re: Spice simulations

I have seen this kind of error before -- are you sure that the model library (*.lib) is being added to your simulation?

v_c

 

[narccizzo]

Re: Spice simulations

look with your own eyes..