Enable/ disable Global interrupt when using EEPROM??

[bikashh]

Hello friends,
I have a question on PIC16F1936, I am using hitec-c compiler and using library read and write functionality for internal EEPROM. My question is, should I disable global interrupt and peripheral interrupts when using read and write functionality for internal EEPROM. I've seen in some codes from the net disabling GIE with EEPROM but they are using pic compiler. Can somebody suggest what to do.
I am afraid the UART interrupt may corrupt the data when writing process to EEPROM is on.

Thanks

 

[betwixt]

Possibly the compiler does it for you anyway so the library routines may give you no choice.
The reason for disabling the interrupts is that the sequence of instructions to remove the write lock has to be followed exactly and if an interrupt diverted the program flow during the sequence it would immediately re-lock the operation and it would fail.

However, all is not lost! The interrupts do not have to be disabled throughout the whole write cycle, you can turn GIE back on again as soon as the write is initiated so in reality the interrupts will only be disabled for a few instruction cycles and the UART FIFO should be able to cope with the backlog. The actual write operation in the EEPROM is quite slow but continues while the rest of the program runs normally, just be careful to check a previous write operation has finished before writing to EEPROM again.

Brian.

 

[T3STY]

Here's a quote from the EEPROM section in the HiTech C Manual:

Note
The high and low priority interrupt are disabled during sensitive sequences required to
access EEPROM. Interrupts are restored after the sequence has completed.

I guess there is no need to manually disable interrupts, the HiTech Compiler will do that by itself. I may be wrong though, so you should check the manual for it (it's the note on top of page 192).

 

[FvM]

It's helpful to bear in mind the reasons for interrupt disable related to EEPROM access. It's required if and only if EECONx control registers are modified during interrupts, e.g. because EEPROM or flash memory are read.

 

[zuisti]

I know this a little differently (from the datasheets):

To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register.
Then a special sequence must be followed to initiate the write cycle:
- write 55h to EECON2
- write 0AAh to EECON2
- set WR bit
A cycle count is executed during the sequence. Any number that is not equal to the required cycles to execute the required sequence will cause the data not to be written into the EEPROM. We strongly recommend that interrupts be disabled during this code segment:

...
BSF EECON1, WREN ; Enable writes

BCF INTCON, GIE    ; Disable Interrupts now !

  MOVLW 55h ;
  MOVWF EECON2     ; Write 55h
  MOVLW 0AAh ;
  MOVWF EECON2     ; Write 0AAh
  BSF EECON1, WR  ; Set WR bit to begin write

BSF INTCON, GIE   ; Enable Interrupts

; other user code execution
BCF EECON1, WREN ; Disable writes on write complete
...

An other solution (without any interrupt disabling) is the Write Verify:
the value written to the Data EEPROM should be verified to the desired value to be written (the EEDATA value before and after writing).

A good news: the EEPROM read does not such sensitive: it is not necessary to disable the interrupt ...