Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Emitter-Coupled Logic -- OR-Gate

Status
Not open for further replies.
H

harry456

Member level 1
Joined
Nov 13, 2012
Messages
39
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,545
Hi, how/why does the or-gate (shown in the pic.) actually work?
Q should be A+B and Q' should be equal to (A+B)' but doesn't this network actually do sth like Q=A'+B'
Thanks
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top