layout of pnp5
Hi ambreesh &
hung_wai_ming@hotmail.com,
thanks for your reply,
I explain why i submit this topic.
In hspice manual:
The scaling of the DC model parameters (IBE, IS, ISE, IKF, IKR, and IRB) for
both vertical and lateral BJT transistors, is determined by the following formula:
ISeff=AREA*M*IS
Ic & Ib are ISeff correlative factor.
This means the paramater "AREA" will affect BJT dc operation point.
In hspice manual:
AREA:Emitter area multiplying factor which affects currents,
resistances and capacitances. Default = 1.0.
AREAB:Base area multiplying factor that affects currents,
resistances and capacitances. Default = AREA.
AREAC:Collector area multiplying factor that affects currents,
resistances and capacitances. Default = AREA.
We can see BJT's gds from foundry clearly.Emitter area is not equal base area and it isn't satisfy hspice default setting.
In calibre LVS:
We need set AREA=25 for pnp5*5 to make LVS correctly.
It confused me the parameter "AREA" is useful to match foundry's measurement or not.
regards,