EM simulation with high resistivity substrate in CMOS IC technology

[vlsi_design2]

Hi, Is there a way to account for high resistivity substrate below inductor in EM simulation software? I am designing an inductor in a CMOS process and using high resistivity substrate layer below inductor to get high Q factor. I have momentum and emx software.

 

[dick_freebird]

First thing is, the HR substrate is suppposed to make high Q and low C
losses as well. But it's baked into the flow up front and if you can get that
wafer built, retail, then all that's been taken care of long since and you
get to just trust the PDK PCells and models. It's not like you get to
change the foundation, only change addresses or don't.

But if you can mesh with material properties that include bulk resistivity
and junction / insulator properties you could examine "whatever" in
simulation. Which of the tools, or both or neither? Couldn't say, myself.