Nurahmad
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* Component pathname : $SIL013_KIT/lib/nmos4 [ELDOSPICE]
*
* .include /EDA/Mentor/sil013_mentor/lib/nmos4/nm_hp
* Component pathname : $SIL013_KIT/lib/pmos4 [ELDOSPICE]
*
* .include /EDA/Mentor/sil013_mentor/lib/pmos4/pm_hp
*
* MAIN CELL: Component pathname : /home/nurahmad/soc/opamp/schem/opamp1
*
CC N$39 OUT 3P
X_M9 N$42 N$42 VDD VDD pm_hp L=0.13u W=2u M=1
X_M6 OUT N$39 VDD VDD pm_hp L=0.13u W=64u M=1
X_M4 N$39 N$14 VDD VDD pm_hp L=0.13u W=16u M=1
X_M3 N$14 N$14 VDD VDD pm_hp L=0.13u W=16u M=1
X_M7 OUT N$42 VSS VSS nm_hp L=0.13u W=30u M=1
X_M8 N$42 N$42 VSS VSS nm_hp L=0.13u W=15u M=1
X_M5 N$10 N$42 VSS VSS nm_hp L=0.13u W=15u M=1
X_M2 N$39 IN+ N$10 VSS nm_hp L=0.13u W=48u M=1
X_M1 N$14 IN- N$10 VSS nm_hp L=0.13u W=48u M=1
*
.end
Hi guys,
Above is the Eldo netlist generated from the Mentor Graphics, this netlist is the conventional CMOS op-amp (OTA) netlist.
Here is question:
Format:
X_M9 N$42 N$42 VDD VDD pm_hp L=0.13u W=2u M=1
Label D G S B Pmos length width ???
What is the last one M=1 stand for? is it the number of fingers?
*
* .include /EDA/Mentor/sil013_mentor/lib/nmos4/nm_hp
* Component pathname : $SIL013_KIT/lib/pmos4 [ELDOSPICE]
*
* .include /EDA/Mentor/sil013_mentor/lib/pmos4/pm_hp
*
* MAIN CELL: Component pathname : /home/nurahmad/soc/opamp/schem/opamp1
*
CC N$39 OUT 3P
X_M9 N$42 N$42 VDD VDD pm_hp L=0.13u W=2u M=1
X_M6 OUT N$39 VDD VDD pm_hp L=0.13u W=64u M=1
X_M4 N$39 N$14 VDD VDD pm_hp L=0.13u W=16u M=1
X_M3 N$14 N$14 VDD VDD pm_hp L=0.13u W=16u M=1
X_M7 OUT N$42 VSS VSS nm_hp L=0.13u W=30u M=1
X_M8 N$42 N$42 VSS VSS nm_hp L=0.13u W=15u M=1
X_M5 N$10 N$42 VSS VSS nm_hp L=0.13u W=15u M=1
X_M2 N$39 IN+ N$10 VSS nm_hp L=0.13u W=48u M=1
X_M1 N$14 IN- N$10 VSS nm_hp L=0.13u W=48u M=1
*
.end
Hi guys,
Above is the Eldo netlist generated from the Mentor Graphics, this netlist is the conventional CMOS op-amp (OTA) netlist.
Here is question:
Format:
X_M9 N$42 N$42 VDD VDD pm_hp L=0.13u W=2u M=1
Label D G S B Pmos length width ???
What is the last one M=1 stand for? is it the number of fingers?