Actually TrickyDicky's example is not quite correct for what you want to do.
Code Verilog - [expand]
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wire[499:0] in_;// for ANDing 4 inputs together and generating an out for those AND'd inputswire[500/4-1:0] out_;integer i;for(i=0;i<500/4;i=i+1)assign out_[i]=&in_[4*i +:4];
&in_[3:0] means bitwise AND the bits together (i.e. it's equivalent to in_[3] & in_[2] & in_[1] & in_[0]). The [4*i +:4] is a bit slice of +4 starting at 4*i so first itteration will give 0 resulting in the slice [3:0], the second itteration will start at 4 giving a slice of [7:4].
|| and && are logical operators and behave the same for single bit operands but are not the same for vectors.
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Actually if all you wanted to do was AND or OR all the inputs together then Tricky's code would do the job, but the code below would the the "right" way to do it.
The above examples are good. As always make sure you understand what a verilog loop is actually doing - the synthesizer effectively unrolls the loop and will instantiate all necessary gates in parallel exactly as if you had typed one giant line with 500 &'s or |'s.
Also with that much logic make sure you understand the timing implications. It's going to be a slow operation (comparatively).